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LVS mismatch on calibre: sub! ;  drain and source sharing issue?

Question asked by swapa001@d.umn.edu on May 17, 2016
Latest reply on May 19, 2016 by swapa001@d.umn.edu

Hello there,

I have made DFF layout in ON semi 0.5um (previous AMI 0.5um) process. The DRC is clean. Now, I am having an issue with LVS in Calibre. (For LVS, I have created netlist from Cadence and input it to Calibre. So, LVS is doing comparison between created netlist and imported gds file.)

 

In layout, I have used sharing source/drain technique. Now, LVS doesn't recognize the shared drain/source net and it makes the mos transistors (with shared drain/source) into a bundle object (_invv,_sup2v,_sdw2v). So, the schematic configuration can not match with layout. Is there any setting, I should try, to prevent this?

 

Moreover, from schematic, calibre takes a global pin "sub!". Although, I have tapped the nwell and pwell in layout for substrate, it seems that LVS cant find any "sub!"  for the series mosfets (it only finds sub! connection for the pmos/nmos connected to vdd/gnd). I have gone through the LVS rule file and tried to change some of the parameters, but couldn't figure it out yet.

 

For your reference, I have attached the LVS summary with rule file including some comments. Can you please check and suggest me what I should do? Thank you very much!

 

 

o LVS Setup:

 

   // LVS COMPONENT TYPE PROPERTY

   // LVS COMPONENT SUBTYPE PROPERTY

   // LVS PIN NAME PROPERTY

   LVS POWER NAME                         "LVCC" "LVDD" "AVDD" "VCC" "VDD" "PS" "vdd!"

   LVS GROUND NAME                        "LVSS" "AVSS" "ASUB" "SUB" "VSS" "GND" "NS" "gnd!"

   LVS CELL SUPPLY                        NO

   LVS RECOGNIZE GATES                    NONE

   LVS IGNORE PORTS                       NO

   LVS CHECK PORT NAMES                   YES

   LVS IGNORE TRIVIAL NAMED PORTS         NO

   LVS BUILTIN DEVICE PIN SWAP            YES

   LVS ALL CAPACITOR PINS SWAPPABLE       NO

   LVS DISCARD PINS BY DEVICE             NO

   LVS SOFT SUBSTRATE PINS                NO

   LVS INJECT LOGIC                       YES

   LVS EXPAND UNBALANCED CELLS            YES

   LVS FLATTEN INSIDE CELL                NO

   LVS EXPAND SEED PROMOTIONS             NO

   LVS PRESERVE PARAMETERIZED CELLS       NO

   LVS GLOBALS ARE PORTS                  YES

   LVS REVERSE WL                         NO

   LVS SPICE PREFER PINS                  YES

   LVS SPICE SLASH IS SPACE               YES

   LVS SPICE ALLOW FLOATING PINS          YES

   // LVS SPICE ALLOW INLINE PARAMETERS    

   LVS SPICE ALLOW UNQUOTED STRINGS       YES

   LVS SPICE CONDITIONAL LDD              NO

   LVS SPICE CULL PRIMITIVE SUBCIRCUITS   NO

   LVS SPICE IMPLIED MOS AREA             NO

   // LVS SPICE MULTIPLIER NAME

   LVS SPICE OVERRIDE GLOBALS             NO

   LVS SPICE REDEFINE PARAM               NO

   LVS SPICE REPLICATE DEVICES            YES

   LVS SPICE SCALE X PARAMETERS           NO

   LVS SPICE STRICT WL                    NO

   // LVS SPICE OPTION

   LVS STRICT SUBTYPES                    YES

   LVS EXACT SUBTYPES                     NO

   LAYOUT CASE                            YES

   SOURCE CASE                            YES

   LVS COMPARE CASE                       NAMES TYPES SUBTYPES VALUES

   LVS DOWNCASE DEVICE                    NO

   LVS REPORT MAXIMUM                     ALL

   LVS PROPERTY RESOLUTION MAXIMUM        32

   // LVS SIGNATURE MAXIMUM

   // LVS FILTER UNUSED OPTION

   LVS REPORT OPTION                      B C D F P S V

   LVS REPORT UNITS                       YES

   // LVS NON USER NAME PORT

   // LVS NON USER NAME NET

   // LVS NON USER NAME INSTANCE

   // LVS IGNORE DEVICE PIN

 

   // Reduction

   LVS REDUCE SERIES MOS NO

   LVS REDUCE PARALLEL MOS                YES

   LVS REDUCE SEMI SERIES MOS NO

   LVS REDUCE SPLIT GATES                 YES

   LVS REDUCE PARALLEL BIPOLAR            YES

   LVS REDUCE SERIES CAPACITORS           NO

   LVS REDUCE PARALLEL CAPACITORS         YES

   LVS REDUCE SERIES RESISTORS            YES

   LVS REDUCE PARALLEL RESISTORS          YES

   LVS REDUCE PARALLEL DIODES             YES

 

   LVS REDUCE C  PARALLEL

   LVS REDUCE C(anmv)  PARALLEL

   LVS REDUCE C(apmv)  PARALLEL

   LVS REDUCE C(pipcnm)  PARALLEL

   LVS REDUCE C(pipcpm)  PARALLEL

   LVS REDUCE schd  PARALLEL NO

   LVS REDUCE schd  SERIES PLUS MINUS NO

   LVS REDUCE enmesq  PARALLEL NO

   LVS REDUCE enmesq  SERIES S D NO

   LVS REDUCE thru  PARALLEL

   LVS REDUCE thru  SERIES TERM1 TERM2

   LVS REDUCE probe  PARALLEL

   LVS REDUCE ext  PARALLEL

   LVS REDUCE v5  PARALLEL

   LVS REDUCE v12  PARALLEL

   LVS REDUCE v20  PARALLEL

   LVS REDUCE v40  PARALLEL

   LVS REDUCTION PRIORITY                 PARALLEL

  

   LVS SHORT EQUIVALENT NODES             NO

 

   // Filter

 

   LVS FILTER C(fillcap)  OPEN

   LVS FILTER C(amisParasiticCap)  OPEN

   LVS FILTER R(amisParasiticRes)  SHORT

   LVS FILTER L(amisParasiticInd)  SHORT

   LVS FILTER D(ppnwd)  OPEN

   LVS FILTER D(nppwd)  OPEN

   LVS FILTER D(nwpsubd)  OPEN

 

   // Trace Property

 

   TRACE PROPERTY  ldd  l l 0.1

   TRACE PROPERTY  ldd  w w 0.1

   TRACE PROPERTY  lddn  l l 0.1

   TRACE PROPERTY  lddn  w w 0.1

   TRACE PROPERTY  lddp  l l 0.1

   TRACE PROPERTY  lddp  w w 0.1

   TRACE PROPERTY  m  l l 0.1

   TRACE PROPERTY  m  w w 0.1

   TRACE PROPERTY  mn  l l 0.1

   TRACE PROPERTY  mn  w w 0.1

   TRACE PROPERTY  mp  l l 0.1

   TRACE PROPERTY  mp  w w 0.1

   TRACE PROPERTY  q  a a 0.1

   TRACE PROPERTY  c  a area 0.1

   TRACE PROPERTY  c  p peri 0.1

   TRACE PROPERTY  d  a a 0.1

   TRACE PROPERTY  d  p peri 0.1

   TRACE PROPERTY  r  l l 0.1

   TRACE PROPERTY  r  w w 0.1

   TRACE PROPERTY  c(anmv) l l 0.1

   TRACE PROPERTY  c(anmv) w w 0.1

   TRACE PROPERTY  c(apmv) l l 0.1

   TRACE PROPERTY  c(apmv) w w 0.1

   TRACE PROPERTY  c(pipcnm) l l 0.1

   TRACE PROPERTY  c(pipcnm) w w 0.1

   TRACE PROPERTY  c(pipcpm) l l 0.1

   TRACE PROPERTY  c(pipcpm) w w 0.1

 

 

 

                   CELL COMPARISON RESULTS ( TOP LEVEL )

 

 

 

                  #   # ##################### 

                   # #          #                   # 

                    #           # INCORRECT     # 

                   # #          #                   # 

                  #   # ##################### 

 

 

  Error: Different numbers of nets (see below).

  Error: Different numbers of instances (see below).

  Error: Connectivity errors.

 

LAYOUT CELL NAME:         DFF

SOURCE CELL NAME:         dff

 

--------------------------------------------------------------------------------------------------------------

 

INITIAL NUMBERS OF OBJECTS

--------------------------

 

                Layout    Source         Component Type

                ------    ------         --------------

Ports:              6         6

 

Nets:              17        18 *

 

Instances:          0        22 *    ME (4 pins)

                    11         0 *    MN (4 pins)

                    11         0 *    MP (4 pins)

                ------    ------

Total Inst:        22        22

 

 

NUMBERS OF OBJECTS AFTER TRANSFORMATION

---------------------------------------

 

                Layout    Source         Component Type

                ------    ------         --------------

Ports: 6         6

 

Nets:               9        18 *

 

Instances:          0        22 *    ME (4 pins)

                     3 0    *    _invv (4 pins)  //each bundle

4         0    * _sdw2v (4 pins) //has two mos

                     4         0 *    _sup2v (4 pins) //(3+4+4)*2 =22

                ------    ------

Total Inst:        11        22

 

 

**************************************************************************************************************

                                  UNMATCHED OBJECTS

       LAYOUT SOURCE

**************************************************************************************************************

 

       ** unmatched port **                             sub! on net: sub!

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