I am using Cadence 6.1.6 with Mentor calibre v2015 3_37.23.
I have a problem when I do the LVS test: in my schematic, I instancied a nmos transistor (width = 960nm with 3 fingers of 320nm each). However, when I perform the LVS test, it considers that I instanciated 3 nmos of 320 nm each and not one single transistor:
M3(-4.090,4.480) MP(PCH_25) MM4 MP(PCH_25)
w: 0.32 u w: 0.96 u 66.7%
Therefore, I have also 2 missing instance errors since it considers I have 3 nch transistors in my layout and only one in my schematic.
Do you know which options I should add to the GUI or to my rulefile in order to avoid this ?
Here is my rulefile setp up:
|LVS SPICE PREFER PINS||YES|
LVS ABORT ON SUPPLY ERROR NO
LVS ALL CAPACITOR PINS SWAPPABLE YES
LVS RECOGNIZE GATES NONE
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE PARALLEL MOS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE SERIES RESISTORS YES //Smashes series resistors
LVS REDUCE SERIES CAPACITORS YES //Smashes series capacitors
LVS REDUCE SPLIT GATES NO //Smashes MOS split-gates.