2 Replies Latest reply on Jul 19, 2016 12:22 AM by matthias.cosaert

    Extremely high current density???


      I am running a DC drop simulation on a 1.2V plane. The plane connects the VRM to 4 pins on a connector and to a bead (that connect to an FPGA).

      The current to the connector (J7) is 2.2A and to the bead flows 0.5A.


      For some reason the bead is not recognized (i think) and Hyperlynx has added a VTP (Virtual Test Point ???).


      I have set the models ;




      The  padsizes for the connector and the bead are more or less the same.  The simulation shows a current density of 1.6A/mm2 for the connector pads.

      but for the bead it shows an current density of 246A/mm2.  I asume that this is caused by the fact that Hyperlynx does not recognizes the bead and add

      a VPT instead ( with no dimensions).


      Does any one of you know what is happening here and how to solve this???



      regards, Charles

        • 1. Re: Extremely high current density???


          probably you can try with defining Bead as resistor because hyperlynx does not recognise Bead.




          • 2. Re: Extremely high current density???



            Try changing the 'Component Types' selection to all in the rop right, then you should see the bead.


            But you shouldn't assign a DC sink model to the bead but define it as a series component since there can be a big voltage drop over them.

            (Sometimes it can be necesarry to use a bead with a higher rated current then needed to lower the voltage drop)


            To assign the bead as as series component:

            - Go to setup Options Reference designator mappings and add the refdes used for your beads as 'Ferrite bead' type.

            - Then in the assign Power integrity models window go to the supply net Inductors tab

            - The bead should be there so enter the DC resistance and hit the assign button.

            - Enable the Include attached nets checkbox.

            - Go to IC tab and assign the DC sink models to the FPGA pins.