1 Reply Latest reply on Jul 21, 2016 1:51 PM by lmccrocklin1

    Assign incorrectly COM Express touchstone models in MultiBoard Project

    hungreohd

      Hi all,

      I'm a newbie in HyperLynx SI. My project is to export s-parameter of high speed nets and get insertion/return loss.

      I have an issue when trying to import COM Express models which connect two board together.

      The COM Express model is 32 ports touchstone model but the real COM Express is 440 pins. So when I import this connector model, I only use 4 ports for SATA_TX_P/N signals.

      Port 1 --> SATA_TX_P (P3's Pin 16 on Board 00)

      Port 2 --> SATA_TX_N (P3's Pin 17 on Board 00)

      Port 4 --> SATA_TX_P (P1's Pin 16 on Board 01)

      Port 3 --> SATA_TX_N (P1's Pin 17 on Board 01)

      Untitled.png

      Per datasheet of connector model, the port assignment is below:

      Untitled.png

      Map schematic pins to S port numbers:

      Untitled.png

      The results of simulation are fail. The insertion loss and return loss are swapped together.

      The return loss:

      The insertion loss:

      I'm very happy if everyone give me any recommendation.

       

      Thank you to all.

        • 1. Re: Assign incorrectly COM Express touchstone models in MultiBoard Project
          lmccrocklin1

          I had an occasion where insertion loss and return loss appeared swapped. They were not really, it just appeared that way. There was a problem in how my dc-blocking caps were routed on the board. My cap pads were on top of the vias (top layer). The green traces are on an internal layer. The pads and vias were physically connected so a fabricated board would work, but the little blue routes from the center of the cap pad to the center of the via were missing. So, Hyperlynx does not see a DC path from the cap pad to the via. Return loss will be 100 % reflection (0 dB) near 0 Hz, and very high insertion loss at low frequency. But Hyperlynx knew there was dielectric around them, so there is an ac path, so insertion loss is finite. This scenario matches your plots.

           

          If this is your problem, I could not find a fix in Hyperlynx; the little blue traces have to be added in the board and the boards translated again.

           

          blocking_caps.JPG