1 Reply Latest reply on Aug 18, 2016 12:55 AM by hans.klos

    ddrx batch simulation timing model assignment

    9dc1212f-cb89-8a24-0100-014e727abccf

      While assigning timing models do i need to create timing models for both controller as well as memory.

      while creating timing models in hyperlynx it asks for various timing parameters.

      Do these timing models are readily available from respective vendor like ibis model

        • 1. Re: ddrx batch simulation timing model assignment
          hans.klos

          For the memory, you can use the supplied timing models in the Hyperlynx library.

          For the controller, you'll need to develop the timing models yourself, based on the timing information in the datasheet of the controller.

          I prefer not to use the default controller model supplied, but always build a customer controller timing model.

          Only for an FPGA this can be more difficult, because the FPGA vendors, don't provide all the timing details for developing a correct timing model.