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ddrx batch simulation timing model assignment

Question asked by 9dc1212f-cb89-8a24-0100-014e727abccf on Jul 29, 2016
Latest reply on Aug 18, 2016 by hans.klos

While assigning timing models do i need to create timing models for both controller as well as memory.

while creating timing models in hyperlynx it asks for various timing parameters.

Do these timing models are readily available from respective vendor like ibis model

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