6 Replies Latest reply on Jun 5, 2018 9:30 AM by newthomasleidenfrost

    Basic hierarchical bus handling


      Hello folks,


      here a basic question that is driving us nuts about handling of hierarchical bus and partial bus.


      Lets start with a simple example: You have a larger bus and would like to rip out two sub busses, half the bit-width of the first.

      In the manual the suggestion is to use a sub bus with a rip net for busses.

      So in a situation that demands that two hierarchical nets are connected to a hierarchical block the resulting design would be something like this:

      In the first block called Matija1 we get the first half of the bus, and in the block Matija2 we get the second half of the block.

      So far so good. All the checks and verifies like DRC-121 do not show any difficulties.


      Let now copy this schematic another time. Now we have four blocks on two schematic pages on the same hierarchical level.



      Same design same logic of exiting the bus.

      A check and verify shows errors on DRC 12 for every single bus net starting form bus0 up to bus15, twice for every net.

      drc-121 - [schematic: Schematic1, bus: bus(7:0)] Missing internal connection symbols on net 'bus0'


      I have no logical explanation why this is an error.

      But wait, there is more...

      If I do not use the bus ripper function, but do rip separate signals one by one, then the single ripped signals are connected to the hierarchical block.

      in picture the it looks like this.



      Now I do NOT get any error for the single ripped signals, but only for the bus ripped ones. (Note the errors start with bus8, no errors for bus0 to bus7)


      Can somebody help us find out why the tool is showing this as an error?


      Many thanks


        • 1. Re: Basic hierarchical bus handling

          It looks like a bug with the checks for 'intra-page' connections and the bus ripper. If you disable the intra-page check in DRC do the errors disappear? From my experiments this appears to be the culprit, can you confirm this?

          • 2. Re: Basic hierarchical bus handling

            Hi Robert,

            From the requseter:

            1) I disabled the "Report extra internal or flat connection on nets" --> Same errors

            2) I disabled the "Duplicate symbols connected on the net" --> Same errors

            3) I disabled the "Hierarchical checks" --> Same errors

            4) I disabled the "Flat checks" -->Same errors

            5) I disabled the "Internal checks" --> No errors

            What is going on?

            Can you explain it and/or can you confrim this is a bug to be taken care of?




            • 3. Re: Basic hierarchical bus handling

              It is a bug, it seems to have been introduced in VX.1. 'Internal checks' tests the on-sheet (intra-page) connections which is where the error is showing up with the bus ripper.

              2 of 2 people found this helpful
              • 4. Re: Basic hierarchical bus handling

                Hello Robert,

                I will open a SR for this.

                In the mean time, I like to tell my engineers to keep designing like this and live with the bug report.


                Thanks for your clarification.



                P.S: And if it possible to add the fix in an update to vx1.2 or greater I would be among the happiest people on earth. :-)

                P.P.S: there was a poll on how many error do you have after finishing a schematic. With this the number jumps up to thousands in our hierarchical design.

                1 of 1 people found this helpful
                • 5. Re: Basic hierarchical bus handling

                  The original issue was picked up in VX.1 and fixed in VX.2 but your use case is subtly different with the repetition of the connectivity. I have logged a defect for it but if you wish to have this back-fitted to VX.1.2 you will have to speak to a support representative and follow their guidelines.

                  • 6. Re: Basic hierarchical bus handling

                    @robert_davies, the issue still seems to exist in VX.2.2, latest update (18).


                    We can't image that no one else has this issue, for example when reusing blocks.


                    When this will be solved? Is there an DR for this already? Bc false positive