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Simulation of edge to tri-state transition

Question asked by kverbeke on Sep 26, 2016
Latest reply on Sep 27, 2016 by Ed Bartlett

Hi all,


The situation:

I'm getting some weird measurements at the output of an LVCMOS output. The output can be high, low or tri-stated becaused it's a shared signal between multiple IC's. At the moment that I'd expect the signal to go into tri-state, a really fast edge occurs which then travels back and forth on the PCB trace, causing large ringing.

The assumption:

Just before the output buffer is disabled, the default high value is already written into the buffer, causing it to put an edge onto the trace approximately 1ns before going into high-Z. Since the PCB trace is now an unterminated transmission line, the edge keeps bouncing up and down and is only attenuated by the trace loss.

The question:

Can I simulate this behavior (fast edge to high-Z) in HyperLynx SI in order to confirm my assumption and try some terminations in order to mitigate the ringing? And if so, how can I do that?


Best regards,

Kjell Verbeke

PCB Test Engineer at Nokia Antwerp