0 Replies Latest reply on Oct 4, 2016 11:46 AM by michael.c.valvo@jpl.nasa.gov

    simulating 8 SDR SDRAM modules bussed together

    michael.c.valvo@jpl.nasa.gov

      hello, I'm struggling to get a good simulation of 8 ISSI IS42S16320B modules bussed together.  I'm hoping that someone has some good advice; it seems that memory cards have lots of memory modules bussed together, so I must be doing something wrong.  The receiver is the A0 signal and the driver is a FPGA pin from Microsemi ProASIC3.  I have IBIS models from the vendors and I'm assuming that all modules are on the top layer and signal routing is on the top and bottom layers and connected with vias.  the clock speed is 125 MHz.   For the simulation, there's lots of reflections at the driver and the receivers look heavily distorted and unusable. I've even tried a simulation where the trace lengths are zero and it still doesn't work.  attached are the schematic and a simulation. any help is appreciated!