We have created a design using a Xilinx FPBGA and two Memory chips. This is a PicoZedboard design.
I am struggling with understanding if our tool can even handle this properly. This is the first time I am trying to route with DDR3 and am overwhelmed with all the constraints, length matching etc.
We use Pads Standard Plus suite, I have all the options. It is version VX.1.2.
First can this tool actually do DDR3 memory routing.
If so, Is there some organized type of order of operations specific for DDR3 routing.
I have setup Pin pair groups, matched length pin pairs. Added my diff pairs, etc.
I do look at the PicoZed design but it is a pdf with no intelligence.
I am learning more about the pads router spreadsheet than I have ever needed to know but I have not made any progress with the routing.
Thanks for any and all help!!!!