11 Replies Latest reply on Nov 17, 2016 6:31 AM by harry-stone

    DDR3 memory routing


      We have created a design using a Xilinx FPBGA and two Memory chips. This is a PicoZedboard design.

      I am struggling with understanding if our tool can even handle this properly. This is the first time I am trying to route with DDR3 and am overwhelmed with all the constraints, length matching etc.


      We use Pads Standard Plus suite, I have all the options. It is version VX.1.2.


      First can this tool actually do DDR3 memory routing.


      If so, Is there some organized type of order of operations specific for DDR3 routing.

      I have setup Pin pair groups, matched length pin pairs. Added my diff pairs, etc.

      I do look at the PicoZed design but it is a pdf with no intelligence.

      I am learning more about the pads router spreadsheet than I have ever needed to know but I have not made any progress with the routing.


      Thanks for any and all help!!!!

        • 1. Re: DDR3 memory routing

          It can route it as interactive. You have already set up your rules. Did you restrict groups to certain layers? I have best success with manual fan out. Then run patterns, route, and optimize at low intensity. This pass usually gets me above 50% competition, if my rules and grid are set right. After that I turn off patterns and step up route to medium, this usually get me to over 80%. Change route to high and it will finish all but the last 10 routes or so, which have to be done by hand. After all routes are in, I go back to work net lengths. Sort spreadsheet by furthest out and work down to smallest. If there is a group to tune, start from the middle and work out. Pick pin pair and tune. Sometimes one trace will bump next one over out of spec. Try picking in different orders.

          I use this strategy on a variety of boards including DDR3 with the PADs BGA suite but same revision as yours.

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          • 2. Re: DDR3 memory routing

            Thanks for the information, I will try you suggestions.


            I find it very difficult to understand how all the rules interact between each other, I know the priorities but it is still difficult.


            I believe I will go back and check my rules to see if I need to change them.

            One other question. I have pin pairs with different length requirements. Is it best to make a pin pair group or create individual matched length pin pairs.

            Ex: One set of nets are called DDR_DQ0 through DDR_DQ31. Is it better to make them all one group and define each pin pair separately or create 32 individual matched length pin pairs.

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            • 3. Re: DDR3 memory routing

              Yes I work with pin pair as a group. Make the longest as short as possible then define lower limit for entire group when tuning length.

              I don't use the matched length feature at all. Route with no length restrictions. Shorten longest trace. Define group length upper and lower length restrictions by longest. Then use tune to get lower up to needed length. If different lengths are needed, I break them into smaller groups. Example DQ0 through DQ7 goes to one chip with one length restriction and DQ8 through DQ15 to another chip with another length restriction etc.

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              • 4. Re: DDR3 memory routing

                That sounds sensible. This is the type of information I was in need of.


                I will break up the nets as you suggest.



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                • 5. Re: DDR3 memory routing

                  In the DDR3 design I am working on I have been given length restrictions for address lines, data lines, control lines,etc.


                  If you normally do not put in length restrictions and route without them how would I tune them for the lengths which are required. Do you put in those lengths later and then try to tune them.

                  I am a little unclear on this.


                  You also said you use pin pair groups but not matched length pin pair groups?

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                  • 6. Re: DDR3 memory routing

                    That is exactly what I do. No restrictions till 100% connected. Then shorten the longest. Apply the length restrictions to the groups. Then go back and tune to final length.

                    I use min and max limits in the pin pair groups to control equal length requirements. Checking the matched length box would tend to keep growing the entire group. Their is always one longest trace in each of my groups with no accordions.

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                    • 7. Re: DDR3 memory routing

                      Thanks this is good information. I am creating pin pair groups as you mention.

                      I have 32 data lines split between two memory chips. i also have a differential pair strobe signal for upper byte and lower byte data of each memory chip which has to be routed on the same layer as the corresponding data signals.

                      So what this means is I have a pin pair group (8 data line signals) and one diff pair strobe signal.I have been able to route either the 8 data signals on one layer but cannot fit the corresponding diff pair strobe signal or vice versa.


                      This is the pin pair grouping I have created for these data signals going from the source part to the memory chips.

                      DDR_Q0-7. Layer 3 plus its diff pair strobe signal

                      DDR_Q8-15. Layer 5 plus its diff pair strobe signal.

                      DDR_Q16-23. Layer 10 plus its diff pair strobe signal.

                      DDR_Q23-31. Layer 12 plus its diff pair strobe signal.


                      I do not know of another way to group them. The diff pairs are not in a pin pair group.

                      I routed the diff pairs without any length restrictions and still could not fit the pin pair group and the diff pair on one layer.

                      I have only tried one pin pair group so far.


                      Any suggestions.

                      Thanks again.

                      • 8. Re: DDR3 memory routing

                        You have the same group set I would use. As I recall you can't add a differential pair to a group, but you can add the same length and routing limits as the group they should be in.

                        I struggle to get them all on the same layer as well. I would suggest getting all pin pairs in before final tuning. I also save design as temporary name before routing. The rules I try at first may need changing to work, this gets me back to no rules and no routes to try again quicker. The more you work with the router the better you can set the rules up front. I use it 2 to 3 times a year so planning ahead could be better.

                        • 9. Re: DDR3 memory routing

                          Another issue I am running across in regards to this DDR3 routing is pin pairs.
                          I have setup my data lines and address lines as pin pairs.

                          The address lines have pin pairs between the BGA (source part) and the 1st memory component. Another set of pin pairs for the same nets that go from the 1st memory chip to the second memory chip.

                          I have routed the address lines between the two memory chips and then created lengths for these, after routing them and then tuned each one to its appropriate length. That worked.

                          Now I am trying to route between the BGA (source part) to the 1st memory chip of these same address line nets. The tool did not always recognize this set of pin pairs and I would go back to Pads layout and add connections. Sometime this worked but sometimes it did not. I also have problems with the system crashing due to pin pairs. Sometimes by clicking on a pin pair the system gives me a message "Run Fault time error." You click ok and the system crashes.

                          Very frustrating.

                          What are the do's and don’ts of pin pairs. I have struggled with this design and cannot find any real documentation on this.

                          thanks for any help again.

                          • 10. Re: DDR3 memory routing

                            I have had this happen as well, but not enough to fully understand why. Here is what I think is happening. When you add the connections
                            they are not automatically added to the group. The existing pinpair is in the group. Non existing pinpair in the group list causes the issue.

                            What I have done in this situation is first make a copy in case you need to go back. Remove all pinpairs from address groups. Using router there is
                            a reschedule command that allow you to redefine pinpair within the net. Get all address unroutes flowing from BGA to memory 1 and memory 1 to memory 2. Then back to layout select pinpair unroutes from BGA to memory 1 and right click make group. There should be an option of add to existing group, which gets your rules back. Using make group in router makes new group without dialog box to add to existing group. Removing all pinpairs from group in beginning stops removed pinpairs listed in group from causing errors and you don’t have to pick thru which ones are changing. Leaving an empty pinpair group preserves rules so you don’t have to reenter rules already set. I have not found a reschedule command in layout. Reschedule command is not showing up for me this morning, not sure why. Have used it to straighten pinpairs to virtual vias flow before assigning to groups earlier this year. Hope you have better results or some one else can help troubleshoot.

                            • 11. Re: DDR3 memory routing

                              My reschedule command for some reason almost stops my system from working. Not sure why.


                              For now I have copied all of my length setup rules to an excel spreadsheet so I know what they are.

                              I am going to proceed with routing without pin pair groups and add them back in later.


                              I will try adding connections in layout, which should allow me to choose that new connection (source component to 1st memory chip) and add to a pin pair group.


                              Thanks for your help. There seems to be many issues and workarounds when working with DDR3 memory and pin pairs.