Understanding the DDRx Design Methodology

Discussion created by min_maung on Nov 1, 2016
Latest reply on Apr 18, 2017 by min_maung

I just delivered a webinar on this topic. In case you missed it, here is the link:

Understanding the DDRx Design Flow Using HyperLynx - Mentor Graphics


In this post, I would like to follow up on some of the questions that came up during the webinar.


The first question was: What is the procedure to perform write leveling?

Here is the link to the TechNote outlining the procedure:


As you will notice, the TN outlines the procedure to do write-leveling between DQS and CLK. The same mechanism can be used for per bit calibration between DQ and DQS as well for both read and write cycles.


The second question was: Does DDRx wizard support 3D via models?

You can create 3D area of the board (such as area around a via breakout) and include those models in the DDRx Wizard simulations within BoardSim without having to export the nets to LineSim. Here is a video on the procedure on how to create a 3D area:



The third question was: How do I include PDN effects in the DDRx Wizard simulations?

Please see the following TechNote on how to enable the SI/PI Co-sim option for DDRx Wizard.


The DDRx Wizard also supports power-aware IBIS models. Please see this TN:



If you have any additional questions on the webinar, please post them here.