As I understand it, what Calibre LFD does is apply optical models for the lithography process to all the squares and sharp edges in your layout to simulate what real, actual smoothed-out shapes will result from it on the wafer after the laser, reticle, and focusing system have done their job. After that, it applies rules to determine when the shapes are too thin or too fat and risk causing shorts, opens, or failures of that nature. The violations of those rules constitute your lithographic hot spots.
So, no, Calibre LFD is not calculating hot spot probabilities any more than a SPICE op point simulation is determining the probabilities of what your DC voltages will be. Like SPICE, it assumes that parameters that have statistical variation in the real world have taken on a specific value and calculates the results based on that.
Now, what can Calibre LFD do? It can do the pretty cool job of figuring out what kind of wavy gravy shapes your sharp-edged layout will give you on the finished chip, so let me anticipate your next question: how do you get Calibre LFD to display that! The answer is a loaded one: it can determine the smooth shapes resulting from your jagged layout, but unless the writer of the Calibre LFD deck enabled you to view these shapes, it won't! A lot of foundries consider those smooth shapes to be information that is too sensitive to let out the door, so they disable the output of the OA file that contains them. Instead, you get the hot spot information, which RVE can display. I think you can also get an OA file if you configure your deck correctly, but the hot spots are just squares, so you might as well let RVE handle it, because then you can see them in your layout editor on top of your layout.
I think I can guess where you're coming from: you ran LFD on your layout and there were no violations, so you're wondering if it actually did anything. Typically, the LFD PDK distributed by the foundry includes a layout that has a violation in it so you can a) see an example of a layout with a violation and b) confirm that you did your compilation and configuration correctly and LFD is working.
I'll close out by addressing the other part of your question: checking regions of the design. I wish I could point you to a specific reference, but I can't find it. When I originally studied the Calibre DFM flow, of which LFD is a part, it appeared the different tools had different scopes in terms of area covered. My memory might be foggy and I might be mixing up which tool is for what, but this is how things work as best I recall. LFD works on small regions, so it makes sense to run it on an instance level. CAA works on larger regions: tens to hundreds of microns, so it makes sense to run it on the sub-systems of an SoC. VCMP checks large regions at millimeter scale, so it makes sense to run it on the chip top level.
Thank you for your answer. I guess that Calibre might calculate the probability because what cause litho hot spots have variation.
I am trying to gathering litho hot spot examples for my research but it is very hard to make many litho hot spots in my design. As a work around, I planned to find layout patterns that have relatively high litho hot spot probabilities and to use the patterns as litho hot spots in my search.
Can you give me any advice on how to generate many artificial litho hot spots in my layout?
Thank you again for your help.
Sorry it took so long to reply, but my answer won't be very helpful, anyway. The answer is no. My team found it very hard to create artificial hot spots. The only thing that we got to work was an example from the foundry. It was distributed with their LFD PDK.