I have a PCB with a mixture of voltages. So I have added net class (called HV) for signals needing 1.25 mm clearance with respect to default (All) signals. They can have the default clearance from other signals in that net class (HV nets to HV nets). This was easy to set up in the class to class rules matrix. But, I can not see how to handle unconnected pins in the HV circuit. They are treated like default nets so they need 1.25 mm against the HV nets. I want them to be treated like HV nets.
Is there a way to do this using the constraints manager? I could add a single node net to the unused pin but not all of the unused pins are shown on the schematic symbol. So i would have to edit the library symbols which is discouraged.
I added a capture of an example. In all of the signals are members of the HV class. They have 1.25mm cleance to other net classes and 0.15mm to other members in the class. Clearance errors are indicated against an unused pin.