Why do planes radiate?The demand for charge at one point on the PCB causes a depleted charge and movement of charge to replace this lack of charge. If the charge delivery system is not damped (and it is not for low resistance planes) then the charge is over drawn and at the point that there was a lack of charge, planes deliver the excess charge and it has to be returned back. This action changes the polarity of the electrical field in the vicinity of the planes and the radiation starts. Because of the un-damped response of a PCB plane, the efficiency of the PCB metal planes as a radiation element is very good, and the gain in certain directions is quite large.
E field will be launched normal to the planes and sideways from the planes. If planes are very close, then the sideway component may be small.
Even if we sandwich the power plane between two ground planes, we can not prevent radiation!
Waves between PWR and GND planes will be launched no matter if the PWR plane is totally enclosed with GND on both top and bottom and on the sides with GND via stitching. As waves are launched, the potential between PWR and GND causes the charge to move on GND and that movement of charge is causing radiation. At the open end of the transmission line, voltage changes from positive to negative and similarly at half wave-length along the line from end, but at a different polarity. We can see how electrical radiation waves start forming. Note the loops of electrical field that start to form in the air.
When a plane wave exists between two plates (GND & PWR), and the planes are unterminated, multiple reflections from plane edges form maximums and minimums of voltages due to superposition. To eliminate or reduce the radiation from the GND shield, we need to terminate the planar waves. In the case of a uniform width transmission line, terminating the line is straight forward. This is not so in the case of planar waves. But it should still be possible to reduce the reflections from the end of the PWR plane and reduce radiation. Shorting the ends of two outside GND planes does not terminate the waves. It just moves the maximum points, it is important to terminate the planar waves between PWR and GND.When a transmission line is properly terminated, only a direct wave exists. Although there are points along the line that have positive and negative voltage potentials, these points are not fixed in placement along the transmission line. These points that exhibit specific electrical potential difference move along the line. So the radiation pattern does not exist because the electric field can not form enclosed loops in the air.
Let's to see what problems in this PBA:
Voltage potential distribution on the plane depends on the frequency of excitation, the geometry of planes and the placement of the source as well as placement of any lumped element. Placement of chips is as important as their current draw. Chips are sources of excitation of the PWR/GND plate system, due to their current draw, but also, they are damping the response as the voltage/current=resistance, so they act as damping resistors. This is why tests that stop or change current draw of one particular chip and using those measurements to determine its influence on radiation of others are not valid. This method is valid for cases where we have individual element radiation, but not in case of metal plates radiation. The only way to check the contribution of a particular chip’s radiation is when all chips are operating in their normal mode and then identify the amount of radiation due to the particular chip. Otherwise, stopping clocks or removing power to particular chip and thereby stopping its current draw, changes the damping effect and will lead to the wrong conclusions.
Designating spurs at 625MHz as 1, 2 & 3. Pressing each chip we can find which chip contributes to which spur
Chip #1 causes spur # 2
Chip #2 causes spur # 3
Chip #3 and Chip #4 contribute to spur # 1
Note:Chip #1 is not the largest contributor
To further illustrate the above statements , simulations show the contours of E field above the two metal planes with 3 sources between the planes. Each source has same amplitude and same internal resistancelTop plot is combined E-field from the 3 sources all of same strength but positioned at different places in the planes. Second plot is E field due to source #1, but with the loading of sources #2 & #3. Third plot is E field due to source #2, but with the loading of sources #1 & #3. Fourth plot is E field due to source #3, but with the loading of sources #1 & #2. The strength of the E field is presented with contours of the same level. The color coding of the lines is such that the red color represents the strongest field and green the weakest. We can see that E field due to each source is different and also has different field strengths due to the other two sources. The damping in all four plots is the same, therefore the position of the source is very important, and the strength of source is not the only factor amount of radiated E field.If we simulate only one source, you see the same effect. The plot on the left shows only one source E fields above the top plane. Plot on the right shows E field due only to the source #1 at the same position as on left side case, but with loading of two other sources. The intensity of the field is represented by different colors. Red represents the strongest field and green the weakest field. We can see that the left side exhibits not only a different E field distribution, but also has a stronger field at certain points than the same strength source but with other sources that are present on the board. Similarly, two plots for source #2. Plot on the right shows E field due only to the source #2 at the same position as on left side case, but with loading of two other sources. Again large difference due to the presence of the loading R of the other devicesThese plots were modeling near field effects of the PCB. Similar conclusions are still valid for far field.The next set of plots show the same source strength but at different positions on planes.You can see an 8 dB difference in absolute strength of Emax just due to placement.
•We can see further that although 2 plots below both have an identical active source at the identical position on planes, the presence of the loading due to the two other sources changes both far field and maximum intensity of E field. •The difference is almost 8 dB. •Comparing the single source plot with previous slide, we see that that source alone produces almost the same E field as all three sources present together. It would be easy for someone to make a conclusion that source 1 is the major source of radiation, but looking at previous slides, in fact source 1 contributes less than source 3.What are the possible solutions? Terminate the planar waves.Reduce the effective length of the radiators by shorting points between two planes that carry the wave
Short the sources so that the excitation is not propagating further. Reduce overall thickness of the PCB and dielectric between the PWR and GND planes.Enclose the PCB with a shield. This shield should not be connected to GND node that is used for carrying charge. Only connection to GND node can be at one point. We recommends using all of the techniques above in tandem.Specifically #1, 2 and 3 together is a recommended minimum requirement.The three solutions are scalable and have an additive effect. If EMI is met with all suggested components, then it will be possible to remove some of the excess components and reduce the excess margin.We can think of a plane as a number of microstrip lines of striplines each next to each other. If each line has characteristic impedance 50 Ohms, then all these lines in parallel will have a much lower impedance. We can see that it is almost impossible to properly terminate the plane with lumped elements but we can approximate. Ideally would be to put extremely large number of resistors at the edge of PWR plane, but this is expensive.
Question is how far apart can we put resistors and what value this resistors on the edge of the board need to be. We can model the plane as bunching several lines together and terminating them with a small resistor. For example 6 lines we can terminate with 8.33 Ohms, and put number of 8.33 Ohm resistors at 6 times the distance of the one 50 Ohms line.
Terminations must be at less than one quarter of wavelength distance. Best results will be for even smaller distances like 1/8th or 1/16th of wavelength.
In FR4 quarter wavelength for 1.25GHz is about 3cm. Quarter wavelength for 625MHz is approximately 6cm. A reasonable and safe distance would be 2cm distance between the two terminating resistors. Note that because terminating resistor needs to be terminating planar wave between the PWR 3.3V and GND, using just a resistor will cause large power draw. This is not necessary as we are only looking to terminate frequencies between 300MHz to 1.25GHz. For that purpose using 1nF capacitors in series with resistor will be effective.
Unfortunately the parasitic series inductance of the 1nF capacitor can be close to 1nH, and resistance can be close to 0.5 Ohms. Also the PCB via inductance portion between PWR plane and bottom and GND plane and bottom can be between 0.4nH to 1nH, and there will be some parasitic resistance due to this portion of via resistance most likely in the order of 0.1Ohms to 0.2 Ohms. This means that the termination effectiveness will be frequency dependent, and of course, the closer the termination resistors, the better the termination, as effective parasitic inductances will be made of more parallel inductances. The termination resistor value should be reduced by the amount of parasitic resistances of PCB via and capacitor contributions. Use about 1 Ohms resistors and 1nF caps in series every 2cm around the edge of PWR plane.
The idea is to put a footprint for terminating R&C every 2 cm. These do not have to be populated if not necessary. Once the measurement of EMI is done it may be possible to install only every second or even third termination.
We can think of the GND plane as a large number of half-wavelength dipoles. Due to the fact that the dipoles will all work as an array, high directivity and large radiation of specific frequencies can be accomplished.Note that dipoles can be oriented in different directions and we can have different sections of the GND plane having different orientation of the dipoles. What we need to do to reduce radiation is to make sure that dipoles can not effectively form. One way to effectively make sure that the dipoles on the GND plane can not form is to install field of capacitors between the PWR and GND planes at some distance. This distance should to be smaller than quarter-wavelength. Again for 1250MHz a quarter wavelength is 3cm in FR4. Diagonal distance of 3cm results in xy distance of approximately 1.5cm. So installing for example 1nF between PWR and GND at every 1.5cm should result in drastic reduction of radiation. We can not use large capacitor values due to their parasitic inductances and resistances, but 1nF should be very effective.l
In below picture, Red circles show the chips that draw current and cause EMI spurs. Blue circles show the shorting capacitors that are effective at this frequencies.
Note that 0.1uF may not be very effective to short the 625MHz or higher frequencies.A 0.1uF capacitor and the PCB via can have a 2nH parasitic series inductance and up to a 1 Ohms series resistance. Series 2nH parasitic inductance at 625MHz has impedance of 7.85 Ohms. So, it can be possible that impedance of 0.1uF cap is almost 10 Ohms at 625MHz. This will not be a very good source of providing charge at 625MHz. It is much better to use several 220pF capacitors as close as possible to the chips that cause 625MHz current draw as shown above
Now we post our workaround simulations:
Using workaround #1 and #2 – termination and capacitor array
E field of same PCB as before but with 24 capacitors 1nF between PWR and GND. Capacitors are arranged in 6x4 matrix. Distance between capacitors is 3cm x 2.75cm.
Model of each capacitor includes 1nH parasitic inductance and 0.5 Ohms parasitic resistance. Also 34 terminations are put along 4 edges of PWR. Resistance is 2 Ohms and cap is 1 nF. Termination distance is 2 cm. Model includes parasitic inductances. We see that in this case max E filed is 47.6 dBuV/m.This means that about 32 dB reduction of E field is achieved
Using Workarounds #1, 2 and 3
Same as on previous slide but now also capacitors that short sources are used. Four shorting capacitors per source. Each shorting capacitor is 100pF. We see that in this case max E filed is 25 dBuV/m.This means that about 55 dB reduction of E field is achieved. On a real board, we may only get 10dB to 20 dB due to the fact that all the discrete capacitors and resistors used in this simulation will be outside the GND shield, and after the plane wave radiation is diminished other sources of radiation will start dominating
Another workaround is to decrease the overall thickness of the PCB and the thickness of dielectric between the PWR and GND planes . Simulating a 25% reduction in thickness reduces the maximum E filed from 25dBuV/m to 19dBuV/m
Aso We have another workaround suggestion:Shieding Plane Closure
Outer shield planes can be connected to GND planes only at the power entrance spot.
GND vias connect only GND but not Shield Planes. Shield planes are connected using a large number of vias on edges, similar to how it is now done now for this board.
Difference is that ground currents cause radiation are no longer on the outer ground planes, as there is almost no current on the shield plane.
The thickness of the dielectric between top/bottom shield and GND plates this can reduce radiation between 3dB to 0dB.
Problem is the capacitive coupling between the GND and outer shield
Once the plane radiation is reduced, EMI from individual elements will begin to dominate.Element radiation should not be overlooked specifically device power delivery and clock signal delivery and effective termination
First, We check the Power Dilivery Network. The red current loop I1 has the fastest edges and highest frequency content. Blue current loop supplies the Cdie with charge that is used for circuit operation. This blue current I2 has to pass through package inductance and portions of the PCB inductances as well through the PCB lumped capacitor parasitic inductances and resistances and this current is filtered and has much lower frequency content. The third green loop supplies the charge from the voltage supply to the PCB capacitors near the chip. The inductance of the PCB is larger than the inductances of the second blue loop and the PCB capacitances so this loop has even lower frequency content, in fact if the PCB capacitances are large enough, the green loop current is almost DC.
Note: L1 and L2 are inductances of package and PCB via from power and ground plans to package.L3 and L4 are inductances associated with the plane inductances from voltage source to PCB decoupling capacitors near chip.Cp is equivalent capacitance of the PCB capacitors near the chip, Rp is equivalent parasitic resistance associated with PCB capacitors and portion of PCB vias from PCB capacitors to power/ground planes, Lp is equivalent parasitic inductance of PCB capacitors and portion of PCB vias from PCB capacitors to power/ground planes.Cdie is decoupling capacitance on the chip.Cpcb is capacitance associated with the PCB planes
We see then that the proper choice of PCB capacitors is very important in determining the EMI. Proper sizing and choice of PCB capacitors will result in I3 current being only a DC current. This current traverses long sections of PCB and it is important to make sure it has only low frequency content. It is important that some of the PCB capacitors designated as Cp1 pose a series resonance at the frequencies that are most harmful and can cause EMI problems. If capacitor have Fr=1/(2 X Pai X Squre root(LP1XCP1))
Then V2 voltage at Fr in respect to GND will be 0 and we will not excite the planar waves. If this is not true, than I2 component at Fr will draw charge from Cpcb and it will start planar waves. This will start charge draw from large distances, and more efficient radiation. The size of antenna is important. Small antenna can only be efficient radiator for very high frequencies.
DDesign rules to minimize element emi radiation contribution are:
1)Good decoupling return paths
3) Clock termination
Many of these are already implemented, but care must be taken to not remove or change the effectiveness of the rule to deal with plane radiation.
PWR and GND vias are key to the return current paths.PCB capacitors near the chip are mounted on top or bottom of the PCB. To connect these capacitors to power/ground plane and the chip we need vias. These vias are important. Each via has an inductance that reduces the bandwidth of the power delivery network, but also voltage drop on the via can cause radiation problems of various kinds. One is that current through the vias launch the waves into the PCB planes. If we make sure that the PWR and GND vias are as close as possible and current is equal in PWR and GND but opposite in direction, then magnetic fields due to PWR current and GND current are opposing each other and reduce launching planar waves. So not only are decoupling capacitors important, but making sure that the each PWR via has a GND via as close as possible.
Decoupling capacitors should not only be of one kind (0.1uF). Beside this capacitor, provide bulk of the required charge and smaller capacitors with lower parasitic inductance and resistance and resonate around important frequencies.
Here is the Decap's return Paths:
A further suggestion to reduce clock element EMI can also be implemented. GND vias around signal vias that carry 125MHz clocks. Use four GND vias around clock vias
.One clock via for each signal via is better than none.Better is to surround clock with four ground vias reducing the chance of planar waves being launched
Now it's time to Clock Termination.
We need to move charge from one chip to another. The GND current has to exist to move charge for charging and discharging Cload.Instinctive reaction is to try to filter the high frequency components and slow down the edges. For example we can put the capacitor C1 to filter the high frequency components during the charge Cload cycle. It will help that but at the same time it will draw much more current from Cdie, and therefore still cause problems as not power supply needs to deliver that charge to Cdie. This is represented with blue current trace on bottom picture. So installing C1 does not solve the problem, in fact, it can make it worse, depending on how well the power delivery is done. Similarly using the C2 will make both sides of line not terminated and that in fact would be a problem, as the wave will bounce between the Cload and C2.
A terminated straight line (no discontinuities) does not radiate because only direct wave is present on the line (or ground) so we do not see points of maximums and minimums of voltage along the path. Unfortunately in this case the load is a capacitor that looks like a short when not charged so the direct wave will be totally reflected. But this reflected wave will be terminated on the return path by Rs+Ron, where Ron is on resistance of bottom transistor. Moving Rs near the Cload does not help because then in discharge of Cload cycle transistor will not be terminated. Only one return path of the wave exists as the Rs terminates the reflected wave. So the formation of the maximums and minimums along the path (including GND plane) exists only temporarily till the Cload gets charged. To prevent the multiple reflected waves and possibility of radiation, it is important to make sure that there are no discontinuities along the transmission line. Extra capacitance or inductance will create the possibility of multiple reflections. For that reason all GND vias need to be near the Clock signal vias, otherwise there will be an extra inductance on the ground plane that will cause reflections.
Optionally, having two series R, one at the source Rs and one near the load (not shown) can be equally effective
Let's back to the begin of story.I don't wish to discuss how effective these old tricks to deal with EMI issue. Just It sounds most of simulation can be accomplished by Hyperlynx PI 8.0 except the 3D EM. ,How well Hyperlynx Perform if used in such cases?
I like to see Steve or Chuck post some insights here.