0 Replies Latest reply on Feb 20, 2017 11:05 PM by malgumhasan@gmail.com

    How to solve "keepout" overlapping  ?

    malgumhasan@gmail.com

      Hi there,

      After placing components inside  generated "keep-out" region of board-outline, its seems like conflicting with my component   "decal"  keepout  area.

       

      If I  click to Tools>  verify design, the error massage says in clear.lst file as,

       

      Error   1 Location 15720,17955 Level 1

      Component Height Keepout violation error:

      J6.1, KEEPOUT(15300,19100) overlapping

      Take a look this image, you could understand whats going on.

      overlapping.PNG

       

       

      Number of question arises,

       

      1. During creating connectors boundary by  2D line, what steps should  I  need to follow ?

      2. Why 2D line of connector here is acting like "keepout"?

      3. If its 4 layer pcb, then what should be "keepout" layer setting, should it be in primary component side or TOP?

      4. If its TOP layer selecting from drop down list, (in drafting properties of keepout)  then what  do you usually set for "Keep-out restrictions"?

       

      Hope you will help me.

       

      Regards

      Hasan