I am facing an error while practicing the reference design of DLP-2232M-G board downloaded from this website.
The design engineer of this board has been used 2 layer (TOP and BOTTOM ) keeping 3 to 21th layer inactive.
Take a look " layer setup", in both case he assigned GND at "Assign Nets".
After I made schematic in PADS logic and connect with PADS layout, I found GND trace on PADS layout design.
Take a look, 2 capacitors ends are shorted, they are "GND". In this design, no layer for "GND" has been called.
Kindly, tell me what should I do and whats wrong am I doing!
If you feel any setting is necessary in "Design rules", let me know.