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Why the GND is visible for 2 layer design?

Question asked by malgumhasan@gmail.com on Feb 28, 2017
Latest reply on Mar 5, 2017 by malgumhasan@gmail.com

Hi Sir,

 

I am facing an error while practicing the reference design of  DLP-2232M-G  board  downloaded from this website.

 

The design engineer of this board has been used 2 layer (TOP and BOTTOM ) keeping 3 to 21th layer inactive.

Take a look " layer setup", in both case he assigned GND at "Assign Nets".

two_layer.PNG

 

After I made schematic in PADS logic and connect with PADS layout, I found GND trace on PADS layout design.

Take a look, 2 capacitors ends are shorted, they are "GND". In this design, no layer for "GND" has been called.

gnd_trace.PNG

 

 

Kindly, tell me what should I do and whats wrong am I doing!

If you feel any setting is necessary in "Design rules", let me know.

 

Thank you.

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