6 Replies Latest reply on Mar 15, 2017 8:02 AM by oawad

    LVS issues with a design from SoC Encounter

    oawad

      Hello All,

      I designed a layout in SoC Encounter using NangateOpenCellLibrary 45nm which had zero geometry and connectivity violations. I then exported GDS file and verilog netlist from Encounter. I went to Calibre to run LVS and afterwards PEX for post-layout simulations.

      Here are my steps:

      1) run v2lvs command "v2lvs -v netlist_encounter2.v -l NangateOpenCellLibrary.v -o netlist_v2lvs.spi -s NangateOpenCellLibrary.spi -s1 VDD -s0 VSS"

      2) I open calibre -gui, attach GDS and spice netlist (from v2lvs) and everything as default....then hit Run LVS.

       

      I then get these errors:

        Error:    Different numbers of ports (see below).

        Error:    Different numbers of nets (see below).

        Error:    Different numbers of instances (see below).

        Error:    Connectivity errors.

        Error:    Property errors.

        Warning:  Ambiguity points were found and resolved arbitrarily.

        Warning:  LVS property resolution maximum exceeded.

      -------------------------------------------------------------------------------------------------------------

      INITIAL NUMBERS OF OBJECTS

      --------------------------

                      Layout    Source         Component Type

                      ------    ------         --------------

      Ports:          11528       390    *

      Nets:           43086     42747    *

      Instances:      41746     41746         MN (4 pins)

                       41746     41746         MP (4 pins)

                      ------    ------

      Total Inst:     83492     83492

      NUMBERS OF OBJECTS AFTER TRANSFORMATION

      ---------------------------------------

                      Layout    Source         Component Type

                      ------    ------         --------------

      Ports:          11528       390    *

      Nets:           16475     16112    *

      Instances:       1903      1691    *    MN (4 pins)

                        1337      1309    *    MP (4 pins)

                         180       180         OAI_3_3 (7 pins)

                         977       977         SPDW_2_1 (4 pins)

                         280       280         SPDW_2_1_1 (5 pins)

                         631       631         SPDW_2_2 (5 pins)

                         360       360         SPDW_2_2_1 (6 pins)

                         120       120         SPDW_2_2_2 (7 pins)

                        1283      1283         SPUP_2_1 (4 pins)

                         301       301         SPUP_2_1_1 (5 pins)

                         440       440         SPUP_2_2 (5 pins)

                         620       620         SPUP_2_2_1 (6 pins)

                         160       160         SPUP_2_2_2 (7 pins)

                        1608         0    *    _invb (6 pins)

                        3328      4936    *    _invv (4 pins)

                          87        87         _invx2v (4 pins)

                        1374         0    *    _nand2b (7 pins)

       

      Here is a link for the my full LVS files: LVS - Google Drive

      These same errors happened with more than one design using the same library "NangateOpenCellLibrary 45nm".

      Please, if anyone can tell me if the problem is with the library or there is something else. 

      Thanks

        • 1. Re: LVS issues with a design from SoC Encounter
          oawad

          I didn't set any initial correspondence points, but I found in the LVS summary report that there are correspondence points set by default. BUT they don't include all my I/O ports, can this be causing these errors ? (see code below)


          If I should set initial correspondence points including all my I/O ports, please tell me how to set it as I don't have experience with Calibre.
          **************************************************************************************************************  INFORMATION AND WARNINGS**************************************************************************************************************

           

            Matched Matched Unmatched Unmatched Component  Layout Source Layout Source Type  ------- ------- --------- --------- ---------  Ports: 390 390 10878 0
            Nets: 4239 4239 11976 11873
            Instances: 640 640 1259 1051 MN(NMOS_VTL)  0 0 1333 1309 MP(PMOS_VTL)  74 74 106 106 OAI_3_3  310 310 667 667 SPDW_2_1  20 20 260 260 SPDW_2_1_1  167 167 464 464 SPDW_2_2  23 23 337 337 SPDW_2_2_1  47 47 73 73 SPDW_2_2_2  890 890 393 393 SPUP_2_1  26 26 275 275 SPUP_2_1_1  29 29 411 411 SPUP_2_2  24 24 596 596 SPUP_2_2_1  37 37 123 123 SPUP_2_2_2  0 0 1609 0 _invb  3327 3327 0 1609 _invv  87 87 0 0 _invx2v  0 0 1368 0 _nand2b  451 451 0 1368 _nand2v  0 0 524 0 _nand3b  80 80 0 524 _nand3v  242 242 0 0 _nand4v  0 0 448 0 _nor2b  920 920 0 448 _nor2v  0 0 430 0 _nor3b  32 32 0 430 _nor3v  181 181 0 0 _nor4v  0 0 285 0 _pdw2b  18 18 0 389 _pdw2v  0 0 282 0 _pup2b  0 0 0 294 _pup2v  0 0 3467 0 _sdw2b  2837 2837 0 3467 _sdw2v  0 0 3174 0 _smp2b  2545 2545 0 3174 _smp2v  ------- ------- --------- ---------  Total Inst: 13007 13007 17884 17768

           

          o Statistics:
            25 source nets were deep shorted to 1.
            302 layout mos transistors were reduced to 134.  168 mos transistors were deleted by parallel reduction.  302 source mos transistors were reduced to 134.  168 mos transistors were deleted by parallel reduction.
            160 nets and 262 instances were matched arbitrarily.

           

          o Layout Names That Are Missing In The Source:
            Ports: SA01[0] N715 W0[18] N228 N413 SA00[4] N194 N48 N1392 N671 N360 N394 N657 N687  N678 N383 N674 N659 N174 N102 N919 N240 N535 N540 N242 N545 N483 N408 N550 N574  N1484 N258 N576 N563 N557 N415 N1523 N412 N1485 N250 N252 N1459 N710 N377 N388  N184 N664 N695 N769 N682

           

          o Initial Correspondence Points:
            Ports: VDD VSS KEY[124] TEXT_IN[112] TEXT_IN[16] TEXT_IN[22] KEY[117] TEXT_IN[118]  TEXT_IN[115] TEXT_IN[114] TEXT_IN[17] TEXT_IN[91] TEXT_IN[90] TEXT_IN[72]  TEXT_IN[74] KEY[76] KEY[16] TEXT_IN[41] TEXT_IN[101] TEXT_IN[106] TEXT_IN[108]  TEXT_IN[125] TEXT_IN[97] TEXT_IN[10] KEY[66] KEY[2] KEY[61] KEY[77] KEY[34]  TEXT_IN[63] KEY[27] TEXT_IN[2] KEY[102] KEY[96] KEY[60] TEXT_IN[61] TEXT_IN[13]  TEXT_IN[6] KEY[5] KEY[67] KEY[32] TEXT_OUT[82] TEXT_OUT[87] TEXT_OUT[17]  KEY[125] TEXT_OUT[22] TEXT_OUT[16] TEXT_OUT[49] TEXT_OUT[21] KEY[122]  Nets: SA01[0] N715 W0[18] N228 N413 SA00[4] N194 N48 N1392 N671 N360 N394 N657 N687  N678 N383 N674 N659 N174 N102 N919 N240 N535 N540 N242 N545 N483 N408 N550 N574  N1484 N258 N576 N563 N557 N415 N1523 N412 N1485 N250 N252 N1459 N710 N377 N388  N184 N664 N695 N769 N682

           

          o Ambiguity Resolution Points:
            (Each one of the following objects belongs to a group of indistinguishable objects.  The listed objects were matched arbitrarily by the Ambiguity Resolution feature of LVS.  Arbitrary matching may be prevented by assigning names to these objects or to adjacent nets).
            Layout Source  ------ ------
            Nets  ----
            X4/1633 Xu0/Xr0/Xout_reg_24_/QN  X4/1626 Xu0/Xr0/Xout_reg_30_/QN  X4/X6511/14 Xld_r_reg/z10  X7/X4986/14 Xdcnt_reg_2_/z10  X4/X6511/13 Xld_r_reg/z9  X7/X4986/13 Xdcnt_reg_2_/z9  X4/X6511/10 Xld_r_reg/z3  X7/X4986/10 Xdcnt_reg_2_/z3  X4/X6503/10 Xu0/Xw_reg_0__24_/z3  X3/X8048/10 Xu0/Xw_reg_0__25_/z3
          • 2. Re: LVS issues with a design from SoC Encounter
            oawad

            I desperately tried to check one std cell of the Nangate 45nm library. So, I tried to run Calibre LVS on one std cell where I used its SPICE and GDS files provided with the library, but I got an error that the bulk of transistors in the layout is not connected to either VDD or VSS (see attached picture)....so this explains LVS error of the different number of nets in my original design.

            Capture2.PNG

             

             

            As Nangate 45nm was developed using NCSU freePDK45nm, I used the Calibre LVS rule file provided with NCSU freePDK45nm since no calibre files were provided with Nangate. When I first run the LVS check using the Nangate 45nm std cell, I got this "ERROR: Rule file precision 2000 is not consistent with database precision 10000 in input file /root/Desktop/AES128bits/NangateOpenCellLibrary/Back_End/gds/AND2_X1.gds" so I went to LVS options and override layout precision to be 2000 as the rule file.

             

            Can this be causing the problem ?

             

            And for the different number of ports error in my original design LVS, I found that for large designs one should specify correspondence points. I didn't and I saw that only SOME of my I/O ports were included by default as correspondence points in LVS. If you know how to set these correspondence points, then please tell me.

             

            Thanks

            • 3. Re: LVS issues with a design from SoC Encounter
              dbyrne

              Hi Omar,

               

              I would recommend you set the following option in your LVS

               

              LVS INJECT LOGIC NO

               

              It will make the errors related to these components a lot easier to debug.

               

                              1608         0    *    _invb (6 pins)

                                3328      4936    *    _invv (4 pins)

                                  87        87         _invx2v (4 pins)

                                1374         0    *    _nand2b (7 pins)

               

               

              In relation to your bulk node problem, it would appear your Logic Cells don't contain Well Taps. You'll need to find a Tap cell in your logic library and add them to the SOC Design, unfortunately you'll probably need to do this before Placement..

               

              Cheers

              Derek.

              • 4. Re: LVS issues with a design from SoC Encounter
                oawad

                Thanks Derek that helped a lot. Concerning the tap-cell issue, I searched before for tap-cells in my std cell library (Nangate 45nm) but didn't find any. I found on the library provider website that they added taps to all Filler cells. Does this mean that Filler cells act now as tap-cells as well ?

                 

                In SoC Encounter, when I go to (place > physical cells > add well tap) I can find the Filler cells as the only option of the cells to add.

                 

                I already added Filler cells to my design (place > physical cells > add Filler cells) and this was the result of LVS....so should I add Fillers again as taps (place > physical cells > add well tap) ?

                • 5. Re: LVS issues with a design from SoC Encounter
                  dbyrne

                  Hi Osmar,

                  If you have Fillers on all standard cells rows then you may be okay. But check that the smallest Filler contains Well Taps. If it doesn't then it might be an idea to add the smallest Filler cell which contains Well Taps as a well Tap. You'll need to set the distance between cells based on the DRC for distance from MOS to Well Tap.

                   

                  If you  currently have issues with transistor bulks it would suggest you've got insufficient Taps.

                   

                  Regards

                  Derek.

                  • 6. Re: LVS issues with a design from SoC Encounter
                    oawad

                    Thank you again Derek for your reply. I'm now sure that Filler cells can fix my problem. But running LVS, I found that Filler cells are not included in the GDS exported from Encounter. I think they should be included in the GDS for the LVS to pass. Do you know how to add them to the GDS ? (I searched the streamOut command, but couldn't find an attribute to include fillers)