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LVS issues with a design from SoC Encounter

Question asked by oawad on Mar 11, 2017
Latest reply on Mar 15, 2017 by oawad

Hello All,

I designed a layout in SoC Encounter using NangateOpenCellLibrary 45nm which had zero geometry and connectivity violations. I then exported GDS file and verilog netlist from Encounter. I went to Calibre to run LVS and afterwards PEX for post-layout simulations.

Here are my steps:

1) run v2lvs command "v2lvs -v netlist_encounter2.v -l NangateOpenCellLibrary.v -o netlist_v2lvs.spi -s NangateOpenCellLibrary.spi -s1 VDD -s0 VSS"

2) I open calibre -gui, attach GDS and spice netlist (from v2lvs) and everything as default....then hit Run LVS.

 

I then get these errors:

  Error:    Different numbers of ports (see below).

  Error:    Different numbers of nets (see below).

  Error:    Different numbers of instances (see below).

  Error:    Connectivity errors.

  Error:    Property errors.

  Warning:  Ambiguity points were found and resolved arbitrarily.

  Warning:  LVS property resolution maximum exceeded.

-------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS

--------------------------

                Layout    Source         Component Type

                ------    ------         --------------

Ports:          11528       390    *

Nets:           43086     42747    *

Instances:      41746     41746         MN (4 pins)

                 41746     41746         MP (4 pins)

                ------    ------

Total Inst:     83492     83492

NUMBERS OF OBJECTS AFTER TRANSFORMATION

---------------------------------------

                Layout    Source         Component Type

                ------    ------         --------------

Ports:          11528       390    *

Nets:           16475     16112    *

Instances:       1903      1691    *    MN (4 pins)

                  1337      1309    *    MP (4 pins)

                   180       180         OAI_3_3 (7 pins)

                   977       977         SPDW_2_1 (4 pins)

                   280       280         SPDW_2_1_1 (5 pins)

                   631       631         SPDW_2_2 (5 pins)

                   360       360         SPDW_2_2_1 (6 pins)

                   120       120         SPDW_2_2_2 (7 pins)

                  1283      1283         SPUP_2_1 (4 pins)

                   301       301         SPUP_2_1_1 (5 pins)

                   440       440         SPUP_2_2 (5 pins)

                   620       620         SPUP_2_2_1 (6 pins)

                   160       160         SPUP_2_2_2 (7 pins)

                  1608         0    *    _invb (6 pins)

                  3328      4936    *    _invv (4 pins)

                    87        87         _invx2v (4 pins)

                  1374         0    *    _nand2b (7 pins)

 

Here is a link for the my full LVS files: LVS - Google Drive

These same errors happened with more than one design using the same library "NangateOpenCellLibrary 45nm".

Please, if anyone can tell me if the problem is with the library or there is something else. 

Thanks

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