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How to do constraint for DDR3 or DR4 designs in Xpedition Vx

Question asked by Rapport on Mar 22, 2017
Latest reply on Mar 22, 2017 by milostnik

I am using DDR4 in my design with different Byte lanes. I want to know how to set constraints for DDR signals in Xpedition Vx.

 

1. How to create pin pair

2. How to assign different pin pairs of same net in different length match group like address & control

If anyone have complete guide for how to set constraints for DDR designs in Xpedition Vx, it would be helpful.

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