3 Replies Latest reply on May 2, 2017 4:24 AM by vinayarora

    Reference Plane For DDR3 interface


      Hello All ,


      I am working on a 6 layered impedance controlled board having DDR3 interface.


      I have a query related to reference place for impedance matching for DDR3 signal .


      Is it compulsory to provide DGND reference plane to all data / address signals ?


      Can I provide VCC reference plane for impedance matching to some of the data / address signals routed in 4th & 6th layer ?


      Please find the below stackup taken into consideration in our design .


      Layer 1 - TOP

      Layer 2 - DGND

      Layer 3 - Signal

      Layer 4 - Signal

      Layer 5 - VCC

      Layer 6 - Bottom


      Best Regards ,

      Parth Sutariya
      Hardware CAD Engineer

      R&D Center


      190, G.I.D.C Makarpura

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