craig.myers

Single Chip 32-bit DDR2 Routing?

Discussion created by craig.myers on Mar 13, 2009
Latest reply on Mar 17, 2009 by carlos-m-monica

So we have a DSP that requires 32-bit DDR2 memory.  We have decided to use a single-chip solution that is newly available from ISSI.  The problem is that I now have 4 banks with 2 overlapping routing lanes because I am lacking the ability to split the banks as in a 2/4-chip solution.  To complicate matters even more, we are incorporating Happy's recommended HDI topology whereas the chip is mounted on Layer 1 with a Ground Plane and NO traces (only uvia in pad).  Layer 2 is the Power plane with microvia to power pins, thus allowing more routing space on the inner layers.  Below that, I have 2 adjacent digital layers in which to route the DDR followed by another GND reference plane.

 

Attached is a screencap of the rat's nest.  Has anyone run into such a beast?  If so, I am all ears!  The DSP app note specs the trace lengths to be Manhattan +/-50mils which is great when the route path is an "L".  In this case, the pins are almost parallel in the DSP and DDR making the Manhatten length a straight line!  The only immediate solution I can see is to add another GND plane between the 2 DDR signal layers to allow routing both in the same bias to avoid crosstalk.

 

Any thoughts/comments/condolences?

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