Done lot of routing in DDR, DDRII, RLDRAM, QDR and you will find that its not very hard to route those.
- First, i wouldnt use layer 1 as plane since if you use it for routing, you will use less vias, so less losses.
- Swap array pins so the traces in layer 1 can arrive to arrays directly.
- Rotate DDR 90º, traces will get somehow longer, but easier to route
- Always try to route all DQ in one layer and Adress in another apart with ground plane
- I would use Layer 1 for small traces (array connection) layer 2 ground plane, layer 3 DQ(*), layer 4 ground plane, layer 5 Adress, layer 6 plane 1.8V
- Put a small plane of VTT in bottom layer in case you have those terminations
- Match delay +/- 50ps
A very important issue is the decoupling of those power planes! Chose the correct capacitors for your board.
Attached you can see a routing that i made while ago, with a virtex5 and 8 memories connected.
No microvias used.
Thats just my opinion..hope it helps a bit.
Virtex5_Memory.JPG 564.8 KB
We need the microvoas anyway because there is a 0.5mm CSP on the same PCB ... so I might as well take advatage of them so I have them. The GND plane on the outer layer is an experiment we have been looking to do for some time. I'm guessing you do commercial PCB's where you only need to pass FCC. We are automotive and are required to pass MUCH more stringent EMI/RFI constraints. Also, by putting the GND plane on top and the Power 2nd, we can use a capacitive dielectric to use embedded capacitance and try to redcuce the amount of discrete capacitance required. I would LOVE to rotate the chip 90 degrees, but all 4 of my banks will cross and the CLK lines are on the side closest to the BGA right now and those being the most sensitive, I'd like them as short as possible.
OK, if you are already moving to another class in fabrication, i agree that you should use those micro-vias.
I work in telecom, so my constraints are EMI/EMC and of course SI.
Sometimes we use have mixed analog/digital on boards and thats gets a bit complicated for the space available in PCB.
Its always a good pratice to fill top and bottom layer with ground with some good clearence from traces, but it doesnt mean you have to use it as ground plane for impedance proposes in layer 2...it just helps in shielding.
"Also, by putting the GND plane on top and the Power 2nd, we can use a capacitive dielectric to use embedded capacitance and try to redcuce the amount of discrete capacitance required."
Joinning power plane with ground plane is a good way to have clean power suplly, but then it will increse layer count if you use layer 2 and 2 for planes.
If you use layer 1 and 2 for planes, the capacitante will not be that good, since the components pads and the small traces to break out of pad to put vias will make the "chesse" effect on that layer.
Embebded capacitors and resistors is a nice aprroch but gets more expensive, it depends on your budget.
We ussually dont use them..since you may need to change the capacitor or resitor to clean a power supply that depends on the frequency of the transmition line.
Simulation will only give you a good aproximation, but you may need to exchage some values in real life.
"I would LOVE to rotate the chip 90 degrees, but all 4 of my banks will cross and the CLK lines are on the side closest to the BGA right now and those being the most sensitive, I'd like them as short as possible."
I have a diferent opinion about this.. since the Clock must have the same delay of data signals (or at least it should be the longest signal if you can make delays inside the other BGA) and we ussually use differential clock that is more "immune" to noise.
I hope everything gets ok for you
Keep up the good work.