I don't think you want to short out the pins through the device body. Instead, try this:
CONNECT M1 ...
CONNECT M2 ...
CONNECT M1 M2 BY V1
depending on what makes sense for the connectivity of your pin layers. Add other layers to these statements as needed to complete the connections to the POS and NEG pins of memr, but don't short the pins through the device layer itself.
It's generally a good practice not to have connectivity on your device seed layers like RR. This ensures the nets connecting to the devices remain distinct.
Thanks for you help. Physically speaking, my device is connected between M1 and M2. The stack is as follows: (M1>RR>V1>M2) where RR is the layer representing the memr device. What I tried to do today is to create derived layer x and y where they represent the intersection between M1 & RR and M2 & RR respectively. Now given these two layers, should I connect them to M1 and M2? if I connect them, the device is still shorted out despite those derived layer? If I do not connect them, it says cannot establish mask connectivity.
Can u explain to me why that is the case?
If there is no connectivity on layer RR, then there is no way to short through devices on that layer. Connectivity can only appear on RR if it is a Connect layer, an Sconnect layer, or it is derived from another connectivity layer using a node-preserving operation. Generally, device seed layers shouldn't have connectivity on them because then they can't be shorted out.
You could create the device pins this way:
connect M1 M2 by V1
// the derived pin layers inherit connectivity from M1 and M2, respectively
rpos = M1 and RR
rneg = M2 and RR
dev memr(memr) RR rpos(p) rneg(n)
You do not want to do this:
rpos = RR and M1
rneg = RR and M2
because then the pin layers inherit the connectivity of RR. If RR has none, then the memr device cannot be formed (device pin layers must have nodal information). If RR has connectivity, these derivations would short out the devices because the pins would have the same connectivity as the device bodies themselves.
Hope that helps,
Now the extraction goes right but the comparison fails. When I look at the schematic drawn from the layout, both memr terminals are shorted together. I am wandering if we write:
connect M1 M2 BY V1
This shorts M1 and M2 by the via which also exists in the same stack with RR. So even through rpos and rneg are now separated, they inherit M1 and M2 connectivity respectively which are already shorted by the V1. So, this creates a short on the memr terminals.
I tried the shielding option:
connect M1 RR M2 BY V1..... such that I break the connection between M1 and M2 whenever there is RR layer. Now the memr terminals are not shorted (i.e. two separate nets) but they are floating. they do not connect to any other devices and where they should have connected is shorted and accordingly there is net discrepancy. something like:
It should be : transistor connects to memr connects to transistor2
But it actually is transistor connects to transistor2 . And memr is floating with two separate nodes.
Do you have any ideas how to resolve that? I am thinking may be because in other place in the rule file M1 connects to M2 thru V1 which is natural in the process so the break I do during shielding is overridden later? do u think that is possible?
My preference is to not rely on shielding in Connect statements.
I may be misunderstanding what your layout contains, but must a V1 polygon mutually intersect the M1, M2, and RR shapes? Can it be some other layer?
Assuming you can't change the layout, then a possible connect set change could be along these lines:
rr_v1 = V1 inside RR // V1 in an RR region; might have to ensure M1 and M2 are also present
route_v1 = V1 not rr_v1 // interconnect V1
connect M1 M2 by route_v1
This could take care of routing connections throughout the design while leaving the RR devices alone. This assumes M1 and M2 don't connect to V1 elsewhere in the rules.
thanks for interacting with me. The lay out does need to have V1 on top of my RR and V1 is inside RR (there centers coincide but V1 is 100x100nm and RR is 300x300nm). The problem I have is really weird. So, it does extract the device "memr" but it assigns to it two floating nodes. something like 3 and 4. these 3 and 4 are not connected with any other element in the extracted layout netlist. And that is when I deliberately break the connection by either shielding or the method u just suggested. If I connect M1 M2 BY V1, it does the same thing where memr is floating but now it is between 3 and 3. So, it short itself. I started to get the feeling that there is something wrong with exporting the layout. Do you know any problems of that sort? do I have to include something in the layout export pretty much like I include the spice model of that device in netlist export file?
If the node numbers of the device pins are different, then that's probably the direction you want to go insofar as pin connections to the RR devices go.
As far as determining why the device pins aren't connected to other design nets, I can only guess. I'd start by using Calibre RVE to load the Mask SVDB Database. Open the layout schematic and find one of your extracted RR devices. Cross-probe the schematic device into the exported GDS/OASIS layout. Then trace the connections from the device pins to metal polygons for the nets that are (presumably) connected to the pins. Are all the metal layers present as you would expect? What about contacts and vias? (It sort of sounds like vias might be missing.)
If net polygons are missing, you'll probably want to verify which layers are being mapped for export from your layout editor.
I actually probed the nets in the RVE window in the extracted layout netlist. when I probe either floating node of the memr device, it actually highlights the correct metal layer in the layout (i.e. if I probe "pos" it highlights M2 and if I probe "neg" it highlights the M1). But when I highlight the shorted net (the one that should not have bee shorted), it highlights both M1 and M2 as if it totally ignores the memr layer. How come the same polygon in the layout can have two nodes assigned to it?
M1-->22 neg terminal
M2-->53 pos terminal
M1+M2--> 72 which is the short that shoud not have been shorted
If your RR device layer has no connectivity on it, it cannot have a node ID. If the pins of a memr device are shorted, the pins will have the same node ID, but the device body itself will not. (I assume you don't have connectivity on RR.) A polygon cannot have two nodes assigned to it.
I suggest opening a service request.
OK. I think I have to do so. Thanks for you help. I truly appreciate you help.