Quite often we have requirements on the maximum (and sometimes minimum) capacitive load for nets in a certain data bus e.g.
The requirements come from our timing analysis where we make assumptions about the net line cap in order to calculate the output delay for the driving ICs.
The assumed net line cap then becomes the requirement when we do our layout.
As I understood from our layout engineers it takes quie a bit of manual work to meet this type of requirements. They have to route the nets, export the resulting caps, and then iterate until they meet the target.
So my question is if there is a way to constrain the min/max net line cap in CES?
Or do you have to make calculations based on the stackup and then constrain the length and width? And is that even possible to make such length constraints, since you get different properties depending on which layer the net is routed in?