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AM335X GPMC AD Muxed read access to NOR like FPGA

Question asked by sparkyjoe on Jun 22, 2017
Latest reply on Jun 30, 2017 by sparkyjoe

I have been trying to get a nucleus driver created for the TI Sitara am335xevm BSP.

 

My device is up and running, we have writes working however a read access does not generate any GPMC clock or other pin activity to the device.  We would expect to at least see the address get driven on the bus.

 

I have correctly set my gpmc clock pin to input enabled.  This seems to be the most common issue but did not pan out for us.  We are not using gpmc_clk pin on the EVM board we have pin mux configured the CSN1 pin to be our clock (AM335X_CTRL_PADCONF_GPMC_CSN1).  the Register value is 0x00000021.

 

Chipselect region 0

GPMC Config 0_1:0x79001201

GPMC Config 0_2:0x00141400

GPMC Config 0_3:0x00060604

GPMC Config 0_4:0x120c140a

GPMC Config 0_5:0x02121a14

GPMC Config 0_6:0x900a0000

GPMC Config 0_7:0x00000848

 

I did break up the GPMC memory section in the am335xevm.c file so I have my true chipselect0 region, no cache did not help read access.

 

                                /* MEMORY REGION 1 - GPMC 0 + 512M is the full space                          */

                                {(VOID *)0x00000000,            /* Physical Start   */

                                 (VOID *)0x00000000,            /* Virtual Start    */

                                 ESAL_GE_MEM_128M,              /* Size             */

                                 ESAL_WRITEBACK,                /* Cache type       */

                                 ESAL_RAM,//ESAL_MEM_MAPPED,    /* Memory type      */

                                 ESAL_INST_AND_DATA},           /* Memory access    */

 

 

                                /* MEMORY REGION 2 - GPMC FPGA CS0 csbase=8                  */

                                {(VOID *)0x08000000,            /* Physical Start   */

                                 (VOID *)0x08000000,            /* Virtual Start    */

                                 ESAL_GE_MEM_128M,              /* Size             */

                                 ESAL_NOCACHE,                  /* Cache type       */

                                 ESAL_RAM,//ESAL_MEM_MAPPED,    /* Memory type      */

                                 ESAL_INST_AND_DATA},           /* Memory access    */

 

 

                                /* MEMORY REGION 3 - GPMC FPGA CS1 csbase=24                 */

                                {(VOID *)0x10000000,            /* Physical Start   */

                                 (VOID *)0x10000000,            /* Virtual Start    */

                                 ESAL_GE_MEM_256M,              /* Size             */

                                 ESAL_NOCACHE,                  /* Cache type       */

                                 ESAL_RAM,//ESAL_MEM_MAPPED,    /* Memory type      */

                                 ESAL_INST_AND_DATA},           /* Memory access    */

 

I don't believe this is a GPMC FSM timing violation, I have gone through the timing rules for the GPMC on this family of devices.

 

Anyone else run into a similar issue?

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