I am new to this community as well as IC station and calibre. Currently, I am doing ASIC flow using ADK design kit. I used Design Architect to generate EDDM view point and had generated the layout in IC station. However, I faced problem with fixing overflow after autorouting. I did my research on how to fix overflow and ended up in vain.
My mehod of fixing overflow now is
1) type "check over" at the IC session.
2) A message will pop out and I select ALL overflows.
3) then I click AutoOvr
4) A small menu bar pop out at the bottom and I click OK
5) A message prompted which say // Note: Enter a valid value for argument: probe_extent (from: Ic/Ample/Argument 03)
There are no input box or whatsoever to input any argument. Also, I dont know what argument do I need to input. I could not solve this and therefore I am currently stuck with this fixing of overflows.I have tried many things but nothing seems to work ...Any help would be greatly appreciated.
On the other hand, I faced DRC errors with simple layout. Im using TMSC 0.35 rules. and I faced alot of DRC errors which I have no experience in fixing it. I would like to know are there any comprehensive tutorial that could teach me how to fix every each of the type of DRC errors ? Tutorial with diagrams would be great.... I tried to search but mostly just mention that all DRC errors must be fix before moving on to LVS verification. Help would be appreaciated. ..
I can be contaced via email at email@example.com....