I have 27 signals that all start from a FPGA and are chained to 4 DDR RAMS. In the CES I created 4 pin pairs and they are all matched to the clock signal.
So all 27 signals are using 4 times the same formula. 6 of the 27 have a formula violation because the length in the violation is not corresponding the actual.
I tried to clear the formula, cleared and updated the actuals but I still keep having these errors.
Any idea how to solve this?