0 Replies Latest reply on Sep 8, 2017 4:57 AM by amitg

    Control of Splice Wire CSA during wire synthesis in Capital Integrator?

    amitg

      Hello,

      How to tackle below scenario during wiring synthesis in Capital Integrator.

      In the below example ,after synthesizing, resultant splice wires are coming as 0.5,1.0 & 2.5 sq.mm but the outgoing wire to the ground terminal is zero CSA. How to control that wire CSA??

      Logic Design:

      LOGIC.PNG

       

      INTEGRATOR DESIGN:

       

      Integrator.PNG

       

      WIRING DIAGRAM OUTPUT:

      WIRE22612 is having Zero CSA.

      One possible solution I could think of is to "Set wire CSA from terminal Pins" but what if ground terminal is specified in range say from 1sq.mm to 6sq.mm.

      wiring.PNG