How to tackle below scenario during wiring synthesis in Capital Integrator.
In the below example ,after synthesizing, resultant splice wires are coming as 0.5,1.0 & 2.5 sq.mm but the outgoing wire to the ground terminal is zero CSA. How to control that wire CSA??
WIRING DIAGRAM OUTPUT:
WIRE22612 is having Zero CSA.
One possible solution I could think of is to "Set wire CSA from terminal Pins" but what if ground terminal is specified in range say from 1sq.mm to 6sq.mm.
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