This may be a silly questions, but should a testpoint cell have a placement outline?
I checked the training libraries and the answer seems to be no, but I just wanted to know for sure before I make the change to my cell.
Typically, I make my TPs with a placement outline the same size as the pad, just to make sure I can check for interference later. It is not required though.
I also shrink my Ref Des text down to a size that the pad obliterates.
Vern Wnek, C.I.D.
Technical Marketing, Xpedition
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That matches what I've been doing.
Where this question stems from is when I try to place them in areas that shouldn't cause an issue, such as just inside the placement outline that is enlarged for rework around a BGA but outside of the body area, I currently have to accept them. Obviously having the testpoint there won't cause a rework issue nor a placement issue, but it prompted me to ponder the "best practice" for the placement outline of the testpoint.
Sr. PCB Staff Designer, CID+
L3 Technologies, Linkabit
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