4 Replies Latest reply on Nov 7, 2017 5:51 PM by hungreohd

    Some confusions when run the DDR4 Batch-Mode


      Dear Experts,


      To run the timing simulation for DDR4, I have implemented the system in the hyperlynx below:

      On the boardsim, DDR4 controller (our chip) is assigned by IBIS model and DRAM DIMM connector is assigned by .EBD model (RDIMM from Micron).

      The stack up is also completed setting.

      Currently, I does not have enough the parameter to build the timing model for DDR4 controller, so I have used the timing model from the hyperlynx library (ddr4_ctl.v). It's similar with DRAM DIMM (ddr4_dram.v).

      I have successfully run this simulation and export the results (including timing, eye diagram for write, read, command, control, address...). With these results, I have some confusions below, I'm looking forward to see the explanations or the recommendations from the experts.

      1/. The IBIS model does not count the Pin Delay in the package while the match length for DDR in the PCB have counted Pin Delay in the package, does this make the error or tolerance when run DDR4 timing simulation ?

      2/. How I can check the DDR4 routing in the PCB based on the simulation results (eye diagram, timing...)?

      3/. To verify the DDR4 routing in the PCB, can I export the S-parameter of DDR4 traces and analysis some parameter such as return loss, TDR, crosstalk ? if not, please show me how I can verify the DDR4 routing in the PCB using hyperlynx ?


      Thank you so much.

        • 1. Re: Some confusions when run the DDR4 Batch-Mode



          My answer from SI-List included here for the record. For more specific details, you will need to provide some data about your models.


          HyperLynx SI uses whatever package model you have defined in the IBIS model that you assign to components in the design. If you want pin-specific package model, then {R, L, C}_pkg parameters are not sufficient. The IBIS model needs {R, L, C}_pin parameters or [Package Model].


          Generally, the connector is expected to be included in the EBD data. Mentor support might help you with your specific model data.


          The timing of the DDR controller is specific to each controller. You need to get the timing information from the controller vendor, and then it is fairly easy to get that data into a component-specific timing model. See the HyperLynx tool documentation or related articles on Mentor Support Center.


          The DDR wizard can be configured to include many SI effects, and save the waveforms. You can review the waveforms after the wizard runs. Another option is to run the DDR bus nets in the batch SI simulator, and then review the simulator report or resulting waveforms.




          • 2. Re: Some confusions when run the DDR4 Batch-Mode

            Dear Mr Weston,


            I have downloaded .EBD DDR4 RDIMM model from the Micron website. But the Micron can not provide the DDR4 register driver IBIS model because they are not authorized. So I can not verify the timing between Address/command and clock for RDIMM using DDR wizard.

            Can you show the how to get the DDR4 register driver IBIS model  for RDIMM ?



            • 3. Re: Some confusions when run the DDR4 Batch-Mode

              Acquiring and validating models is always a big part of SI analysis. Unfortunately, there is little that we can do to help in this task. I suggest you find the manufacturer of the register IC. Micron should be able to tell you the manufacturer and part number. Then go to that manufacturer to request the IBIS model. If they don't provide it, the next best option is to find the model for a compatible part.

              • 4. Re: Some confusions when run the DDR4 Batch-Mode

                Dear Mr Weston,


                I contacted to the Micron and IDT. They had already provided the RCD part number.


                Thank you so much.