AnsweredAssumed Answered

Some confusions when run the DDR4 Batch-Mode

Question asked by hungreohd on Oct 31, 2017
Latest reply on Nov 7, 2017 by hungreohd

Dear Experts,

 

To run the timing simulation for DDR4, I have implemented the system in the hyperlynx below:

On the boardsim, DDR4 controller (our chip) is assigned by IBIS model and DRAM DIMM connector is assigned by .EBD model (RDIMM from Micron).

The stack up is also completed setting.

Currently, I does not have enough the parameter to build the timing model for DDR4 controller, so I have used the timing model from the hyperlynx library (ddr4_ctl.v). It's similar with DRAM DIMM (ddr4_dram.v).

I have successfully run this simulation and export the results (including timing, eye diagram for write, read, command, control, address...). With these results, I have some confusions below, I'm looking forward to see the explanations or the recommendations from the experts.

1/. The IBIS model does not count the Pin Delay in the package while the match length for DDR in the PCB have counted Pin Delay in the package, does this make the error or tolerance when run DDR4 timing simulation ?

2/. How I can check the DDR4 routing in the PCB based on the simulation results (eye diagram, timing...)?

3/. To verify the DDR4 routing in the PCB, can I export the S-parameter of DDR4 traces and analysis some parameter such as return loss, TDR, crosstalk ? if not, please show me how I can verify the DDR4 routing in the PCB using hyperlynx ?

 

Thank you so much.

Outcomes