2 Replies Latest reply on Nov 2, 2017 12:56 AM by 9dc1212f-cb89-8a24-0100-014e727abccf

    DDRx batch simulation in mentor graphics Hyperlynx

    9dc1212f-cb89-8a24-0100-014e727abccf

      Hi everyone

       

      I am performing Batch simulation in Hyperlynx of DDR4 and want to know about the timing models.

      Does anyone have document regarding these timing models it will really help me out to confirm the Timing parameters in designed board.

      I generated the report based on JEDEC specifications most of the timing results are failing.

       

      Thanks