10 Replies Latest reply on Nov 22, 2017 1:05 AM by hungreohd

    Missing driver model in Generic Batch Simulation

    hungreohd

      Dear the experts,

       

      I use the Generic Batch simulation to run the crosstalk quick analysis for DDR4 in the board sim.

      I have met the issue below:

      I have implemented all workaround base on below link but this issue still happen.

      https://support.mentor.com/en/product/861057060/knowledge-base/MG59549?pid=sc%3Asearch&pid_context=%2A%2A%20Warning%28Se…

      I am very glad if the expert give me some advises for this issue.

      Thank you so much.

        • 1. Re: Missing driver model in Generic Batch Simulation
          weston_beal

          Hung,

           

          From your description and screen capture, it's not clear what you are doing. Your text says crosstalk quick analysis, but the image shows results of the detailed simulation mode. It can be confusing because you can run both in the same batch setup. Then the results might be confusing. Please check that you have selected only the quick analysis (indicated in red) in the Batch Wizard and not the detailed simulations (indicated in blue).

           

          The quick analysis does not require models, so it should not report a problem regarding models. The detailed simulations run actual simulations, so require models on all pins on all the nets that might be part of the simulation. This includes all the pins on all the nets you select for simulation AND all the pins on all the nets that are coupled to the target nets.

           

          If this does not answer your question please provide more details about the steps you take to get to the report.

           

          Regards,

          Weston

          • 2. Re: Missing driver model in Generic Batch Simulation
            hungreohd

            Dear Mr Weston,

            You are correct, I have checked in the detail simulation. Now I have gotten the quick analysis of crosstalk.

            But I have one more concern below:

            I set 23mV threshold so see the crosstalk.

            This value is calculated below:

            23mV = 5% {Switching range for DDR4 (450mV)}

            Is it correct setting ?

             

            I also show the steps which i set up to run the quick crosstalk analysis. I hope you can help to check and give me advice if there are any issues.

             

             

             

            Thank you so much.

            • 3. Re: Missing driver model in Generic Batch Simulation
              hungreohd

              Dear Weston,

              I have one more concern. As you see the rise/fall time which i have configured above, it is calculated below:

              Assume the data rate of DDR4 run at 2666MT/s, the rise/fall time ~ (1/2666)/5 = 75ps. I chose 100ps for rise/fall time setting because it is the minimum value which hyperlynx allow to import.

              Is it correct ?

              Thank you so much. 

              • 4. Re: Missing driver model in Generic Batch Simulation
                weston_beal

                This method of calculating rise/fall time is OK if you can't find better information. It would be better to get the rise/fall time from the part datasheet or an IBIS model for the part. In the case of a bi-directional net, like DQ, use the faster time of the two devices on the net (bus). Actually, if you have IBIS models, you should assign them. I'm pretty sure that the quick analysis will get the driver and receiver parameters from the assigned models. The default IC parameters are used in the cases where no model is assigned.

                • 5. Re: Missing driver model in Generic Batch Simulation
                  hungreohd

                  Dear Mr Weston,

                   

                  I'm running DDR4 Batch simulation with Micron's RDIMM. I use .EBD model.

                  I had RCD IBIS model (ex. 4RCD0124KC0) but I lack of the RCD timing model.

                  I see that Hyperlynx do not support to create the RCD timing model.

                  How to create the RCD timing model in Hyperlynx ?

                  I only look up the RCD timing model for DDR3 (ddr3_pllreg.v) in Hyperlynx library, there is lack of RCD timing model for DDR4 (ex. ddr4_pllreg.v)

                  Thanks.

                   

                  • 6. Re: Missing driver model in Generic Batch Simulation
                    weston_beal

                    Hung,

                     

                    Notice that the .V files are text. Their format is a subset of Verilog. You don't have to use the Timing Model Wizard to edit these files. The Wizard is just a tool.

                     

                    In this case, I suggest editing the file. Make a copy of ddr3_pllreg.v to ddr4_idt_pllreg.v. Open this new file in a text editor. Read the comments to understand the variable definitions. Then you can edit the values in your new file according to the timing information in the RCD data sheet. Notice how the speed grades are defined in the .V file, and you can extend that list to the higher speeds for DDR4.

                     

                    You can also use the Ideas section of this website to suggest the addition of this and more timing models for future releases of HyperLynx.

                     

                    Regards,

                    Weston

                    • 7. Re: Missing driver model in Generic Batch Simulation
                      hungreohd

                      Dear Mr Weston,

                      I had suggested to add the RCD timing model for DDR4 in the Ideal section.

                      There are differences between DDR3 and DDR4 when build the RCD timing model.

                      A DDR3 register timing model is defined by setup and hold time parameters. While DDR4 register timing model is defined by eye mask.

                      About tJIT, tSKO, tDPO, tPDMmin, tPDMmax parameter, I have found them in the IDT datasheet.

                      Do I have to define the new parameters to replace for tDS, tDH? and what are these parameters ?

                      Thanks.

                      • 8. Re: Missing driver model in Generic Batch Simulation
                        weston_beal

                        Specifying a data eye mask assumes something about a clock; either that the clock is recovered from the data stream, or that the clock is probably centered somehow in the eye. Based on the assumption that the strobe is delayed by the RCD to center it in the data eye, we can transform the eye width requirement into setup and hold requirements. Just split the eye width into 2, and assign half to setup and half to hold time requirements.

                         

                        It would be nice to have an eye width specification in the timing model format, but that is another issue.

                        • 9. Re: Missing driver model in Generic Batch Simulation
                          hmbui@apm.com

                          Dear Mr Weston,

                           

                          I have modified ddr3_pllreg.v to ddr4_pllreg.v based on IDT (4RCD0229KB1) and JEDEC spec.

                          I have set up the DDRx Batch-Mode to run timing for Data, clock-to-strobe and Address/command.

                          Currently, my account on Support Net is still locked. I had contacted to technical support but they have not solved for me.

                          So I was concerned about some configuration steps but I can not search the answers on Support Net.

                          I hope you will take a look at my configuration below:

                          1/. PLLs and Registers section

                          Can you show me where I can take the effective PLL clock input to DRAM/Register Clock Input Delay ? (ex. RDIMM datasheet or JEDEC spec...)

                          2/. Nets to Simulate section

                          Can you please explain how does Hyperlynx work to run Data/Clock/Address/Command timing ?

                          How can I see the relationship between timing simulation results with DDR routing on the real PCB ?

                          Example: When I run crosstalk in Generic Batch mode, I can extract some traces which have HIGH crosstalk level, and recommend layout team to modify spacing or routing off.

                          Note that: I am using .HYP file which is translated from .BRD file. .EBD model is used for RDIMM.

                           

                          Thank you so much.

                          • 10. Re: Missing driver model in Generic Batch Simulation
                            hungreohd

                            Dear Mr Weston,

                             

                            The above questions are written by me. I forgot logout my colleague account.

                             

                            Thanks.