Dear Technical Supporter,
I am using Hyperlynx 9.4.2 but there is lack of the RCD timing model for DDR4 (ddr4_pllreg.v).
I suggest to add this timing model to latest Hyperlynx version when it is released.
I have a follow up question. Where I can get either a timing model or template/ guide on how to come up with the timing model for the RCD part?
Hung and Alex - thanks for your questions. This community is for general questions and suggestions for the overall community. Your questions are specific to HyperLynx so I am going to move it to that appropriate community so it will receive greater visibility.
It looks like Hung's original post was a suggestion for improvement that should be in the Ideas place. Can you move that over there?
There is an existing timing model for DDR3 that you can use as a template. The file is in the model library (...\SDD_HOME\hyperlynx\Libs) and is named ddr3_pllreg.v.
There is a timing model wizard in the HyperLynx installation directory. This is intended to create controller timing models, but you can use it to write a model file to help you understand the text of the timing model files.
I hope that helps with your modeling tasks.
I wondering it there is a plan to generate a template ddr4_pllreg.v to avoid any error that could be created by using a combination of a timing model wizard and ddr3_pllreg.v.
An app note or example would be very helpful too.
There is no plan to create a standard ddr4_pllreg.v timing file. The timing calculation needs to be adjusted for each design. There is some good information about this in this article on Support Center.
The last part of the article talks about DDR3, which is more applicable to the DD4 case. For updates on this issue, you can monitor Hung's idea at Add the DDR4 RCD timing model in the latest Hyperlynx release
Thank you, I will check the article.
It was suggested to refer App note MG501664 for creating the DDR4 RCD timing model.
However when trying to apply the recommendations to DDR4 RCD, there is lack of clarity which I have summarized below:
Can you please help answer below three specific queries with respect to tDPO parameter required in the DDRx wizard?
1. Does tDPO in DDR wizard correspond exactly to JEDEC (JESD 82-31) parameter tdynoff?
2. Can I ignore below statement in MG501664 ( Creating a PLL DDRx Wizard Timing Model for an RDIMM")?
"tDPO should include all the timing variations that the PLL device might introduce into the clock signals on the DIMM. These variations are usually labeled static phase offset, dynamic phase offset, and period jitter in the PLL data sheet. These effects are combined in their effect on the timing margin. Therefore, you should add them together to define the value of tDPO in the timing model."
3. If not should I add JEDEC (JESD 82-31) parameters tstaoff, tdynoff, tjit(per) to get tDPO required by the DDRx Wizard?
Providing a sample ddr4_pllreg.v for the DDRx wizard will really help avoid above confusion.
Per Weston's earlier comment, please post your idea here: Mentor Ideas for Simulation and Analysis
I have just posted in Mentor Ideas section.
You can contact to IDT to get the RCD datasheet and then you can build the RCD timing model based on ddr3_pllreg.v template as Weston's recommendation.
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