2 Replies Latest reply on Jan 2, 2018 1:15 AM by hungreohd

    DDR4 CLK/ADD/CMD and Control Termination in UDIMM EBD model

    hungreohd

      Dear everyone,

      I use UDIMM EBD model to run the DDR4 timing in Hyperlynx Boardsim.

      In the UDIMM EBD model, there is the important note below:

      I had checked in the UDIMM EBD model. 36ohm resistors was already in .EBD file but there is lack of 0.01uF cap.

      I don't know how to add the 0.01uF cap and connect to VDD pin in the UDIMM EBD model.

      Similar with ADD/CMD and Control signals, I also want to terminate them to VTT as block diagram below:

      I attached UDIMM EBD model for double check.

      Thank you so much.

        • 1. Re: DDR4 CLK/ADD/CMD and Control Termination in UDIMM EBD model
          weston_beal

          Hung,

           

          This can be a complex problem. EBD file format was a great idea, but it has limitations with differential termination. The most simple and accurate solution it to ask Micron for the HYP file for the DIMM layout. They used to do this, but I don't know how difficult it is to get that. With the HYP file, you can build a multi-board system and simulate the nets directly.

           

          Another option is to assign the EBD as-is in your BoardSim design and export the clock nets to LineSim. In the export dialog, make sure you select the option to expand into the EBD.

          This will create a rather large and messy looking schematic, but it gives you access to all the nodes inside the EBD. That way you can apply the correct termination. This is fine for signal integrity evaluation, but not handy if you want to run the DDR wizard. For that, I would find a way to adapt the EBD to make it work in BoardSim.

           

          In the LineSim schematic, I would see if I could adjust the termination to something like a resistor connected to a constant voltage (Vdd/2) and get the same signal response. This works on the assumption that the motherboard and DIMM have very good differential routing. With a modified EBD I could use the EBD in BoardSim and run the DDR wizard.

           

          I hope this gets you further down the path of successful simulation.

           

          Regards,

          Weston

          • 2. Re: DDR4 CLK/ADD/CMD and Control Termination in UDIMM EBD model
            hungreohd

            Dear Mr Weston,

            I had gotten HYP file from Micron and verified successfully UDIMM timing at 2666MT/s.

            Thank you so much.