Are there any more details about the error in the transcript window of the layout viewer?
I am sorry for the late reply and thanks for the responding. I ahve figured out the issue what is related. It is the issue with pdk which was given by pdk supplier. Now, it is DRC free. But not LVS free. I have simply taken capacitance itself as schematic. When I run LVS, it is giving some warnings which i am not able to figure out what is.
I am attaching the snapshot of warning.