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unable to simulate

Question asked by uzmeed on Dec 29, 2017

Hi

 

As a fist step towards learning TLM I am trying to simulate the code given in mentor graphic tutorial

 

"Utilizing SystemC for Design and Verification"

 

www.edadirect.com/docs/Using_SystemC_for_Design_Verification.pd

 

but getting  the following error

 

C:/Xilinx/Vivado_HLS/2015.4/win64/tools/systemc/include/sysc/communication/sc_fifo.h:314:13: error: no match for 'operator<<' in 'os << *(((cmd*)((const sc_core::sc_fifo<cmd>*)this)->sc_core::sc_fifo<cmd>::m_buf) + ((unsigned int)(((unsigned int)i) * 16u)))'

 

 

Please help me in this regard

 

Best Regards

Uzmeed

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