The usual reason for for the parallel testbench to fail when the serial passes is due to the to the way the parallel testbench loads the scan data into the registers. It releases the data at the end of the cycle in accordance to the timing defined in the shift procedure where the serial testbench simulates the full load and unloading of the scan chains. You can use the parameter "SIM_DELAY_SCAN_RELEASE" to delay this release so that the testbench will simulate properly.
More information can be found in the documentation here:
If you need more detailed information or if this does not resolve the issue, please feel free to open an SR and we will be happy to help.