I am confused by the places used by the Expedition tools to output the simulation files for HyperLynx.
If you are doing a schematic design and export single nets for SI, they will be placed in <design_dir>\HighSpeed\HyperLynx\PreLayoutLineSim
If you are exporting a design for SI in Expedition Layout the board will be placed in <design_dir>\PCB\Output, where I would expect it to be in <design_dir>\HighSpeed\HyperLynx\PostLayoutLineSim
Data for HLDRC goes into <design_dir>\PCB\Output\HLDRC
A lot of directories, some empty by default...
Is this a bug, a feature or something in between?
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