I had run DDR4 DATA timing with Hyperlynx (DDRx batch in Boardsim) and SystemSI (Cadence Sigrity).
The result simulation are so different between two software. I detected the reason of this difference below:
In the SystemSI, when I enable package parasitics parameter, the output signals are below:
In the Hyperlynx, per my understanding, R_pin/L_pin/C_pin will be imported to simulation by default. Note that, my IBIS DDR controller only contain R_pkg/L_pkg/C_pkg and R_pin/L_pin/C_pin, not include [Define Package Model] section.
Can anyone help to understand this difference ?
Thank you so much.