5 Replies Latest reply on Feb 23, 2018 7:26 AM by weston_beal

    Difference between Hyperlynx vs SystemSI about R_pin/L_pin/C_pin in IBIS model

    hungreohd

      Dear Experts,

      I had run DDR4 DATA timing with Hyperlynx (DDRx batch in Boardsim) and SystemSI (Cadence Sigrity).

      The result simulation are so different between two software. I detected the reason of this difference below:

      In the SystemSI, when I enable package parasitics parameter, the output signals are below:

      In the Hyperlynx, per my understanding, R_pin/L_pin/C_pin will be imported to simulation by default. Note that, my IBIS DDR controller only contain R_pkg/L_pkg/C_pkg and R_pin/L_pin/C_pin, not include [Define Package Model] section.

      Can anyone help to understand this difference ?

       

      Thank you so much.

        • 1. Re: Difference between Hyperlynx vs SystemSI about R_pin/L_pin/C_pin in IBIS model
          weston_beal

          Hung,

           

          Just looking at the shapes of the waveforms I will offer a hypothesis. Maybe you can test it later since I don't' have access to SystemSI. It appears that the package model in SystemSI is implemented as ideal R, L and C components. This circuit behaves as a low-pass filter so the signal edges are slower. The RLC package model in HyperLynx SI is represented by a transmission line whose impedance and delay are calculated from L and C. Thus the signal edge is faster and shows the reflections more clearly.

           

          If you increase the L and C values in the package model then the effects that I described will be accentuated. This way you can test my theory.

           

          Regards,

          Weston

          • 2. Re: Difference between Hyperlynx vs SystemSI about R_pin/L_pin/C_pin in IBIS model
            hungreohd

            Dear Mr Beal,

            I have check impedance and delay time in the package file. It is consistent with R_pin/L_pin/C_pin in the IBIS model.

            I still have not understood why SystemSI consider R_pin/L_pin/C_pin as Low-pass filter. I will double check with Cadence supporter later and feedback to you.

            I want to verify DDR4 timing with full channel based on below structure:

            Controller --> Package --> PCB board --> DIMM connector --> DIMM board --> DRAM

            I have two options to modeling the package. That are using R_pin/L_pin/C_pin in IBIS model and extracting S-parameter directly from Package file (.mcm file - Cadence). Which is more accurate ?

             

            Thank you so much.

            • 3. Re: Difference between Hyperlynx vs SystemSI about R_pin/L_pin/C_pin in IBIS model
              weston_beal

              Hung,

               

              The lumped element RLC model acts as a low-pass filter because the inductance is in series and the capacitance is in parallel with the signal path. That is a simple low-pass filter. If the L and C are converted to Z and delay of a transmission line, then the circuit is different, but probably better represents the actual device.

               

              If the package model that you have is already reduced to single stage RLC then extracted S parameters cannot be more accurate. They can only get less accurate. If the MCM file has multiple stages of R, L, and C elements, then the useful bandwidth of the model is higher, but still has a low-pass filter effect. Extracting S parameters of that circuit doesn't help the accuracy. Extracted S parameters can keep the same accuracy as the original model or decrease the accuracy. It depends on how you extract the S parameters.

               

              Getting the MCM or S-parameter files into the simulation uses the same method, so I would keep the MCM file.

               

              In release VX.2.3 there will be a new feature to control coupling from package models if the package model is a Touchstone (S parameters) file. For that specific case, it will be better to use a carefully extracted Touchstone file.

               

              Regards,

              Weston

              • 4. Re: Difference between Hyperlynx vs SystemSI about R_pin/L_pin/C_pin in IBIS model
                aleksandr.kupchik@oracle.com

                Hello,

                 

                I have a follow up question  regrading packages R/L/C and what affect it could have on simulation. Let's say  have two different IBIS models and one has a higher package C value (also a higher L to keep the impedance under control). Should I expect to see a slower rising edge due to the higher C?

                 

                Alex

                • 5. Re: Difference between Hyperlynx vs SystemSI about R_pin/L_pin/C_pin in IBIS model
                  weston_beal

                  Alex,

                   

                  The answer depends on more than then L and C values. First, remember that every interconnect is a transmission line. If a transmission line is very short (< Tr / 20) compared to the signal edge going through it then a lumped L and C can very closely represent the transmission line. As the line gets longer or the signal edge gets shorter then the LC model becomes less accurate at modeling the transmission line. Then the model needs to be a distributed model as an ideal transmission line model. When the line gets yet longer then losses are significant (again depending on relation to signal edge time) and the model needs to be a lossy transmission line model.

                   

                  So, back to your original question, assuming that you are using HyperLynx SI the L and C will be used to calculated the impedance and delay of a transmission line model. The impedance in both package pin models is the same, but the delays are not. Neither of these parameter directly affect the rise time of the signal going through the lossless T-line model. When you get to the point where T-line losses are significant then it's the losses that degrade the rise and fall times.

                   

                  Regards,

                  Weston