I am using Calibre LVS for the first time and I am using it while trying to follow the design flow document which comes with the 180nm PDK from TSMC. I am having an issue with my two stage buffer. I am attaching the LVS report, the schematic and the layout itself here. I generated the layout from the schematic source itself using Cadence's layout XL. All the pins and ports have labels associated with them in the layout but I still get error when compiling the LVS when it comes to the number of ports. I am also getting different number of instances (both PMOS and NMOS) which is stemming from the fact that I am using multifingered transistors.
Again I am using calibre for the first time. Any help in resolving these error messages is appreciated.