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DDR2 batch simulation

Question asked by sureskak on Mar 21, 2018
Latest reply on Mar 21, 2018 by weston_beal

Hi all,

I am performing a DDR2 batch simulation.I am assigning the IBIS models to DDR2 and controller. I have assigned prog buffer 2 model to controller MPC 8323. Address and control nets which are to be configured as output are being configured as input. Model assignment is not being done properly. Please suggest me how to configure the address and control nets as output.


Controller pin: U1.AD11  (MEMC_MCAS_B)  --Model is input only, but needs to be output or I/O

I am also facing another issue which says model does not have receiver thresholds section.


Model does not have a [Receiver Thresholds] section.

Missing Vinh and Vinl thresholds in the [Model Spec] section.