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Hyperlynx DRC Stackup Issue? Or a bug?

Question asked by andreasdietz on Mar 23, 2018
Latest reply on Mar 28, 2018 by weston_beal


I'm working with Hyperlynx DRC Free Edition 6.5.1 and obviously I'm running into an issue when working with an imported layer stackup. The import command loads successfully my PCB stackup:

But when I save the project file and reopen it, the stackup seems to be scrambled:

Any ideas? Do I have a buggy stackup or is it a HLDRC bug?

Even more interesting, the simulation works only with the "scrambled" stackup. With the original stackup the program crashes immediately.