4 Replies Latest reply on Mar 28, 2018 1:58 PM by weston_beal

    Hyperlynx DRC Stackup Issue? Or a bug?

    andreasdietz

      Hi,

      I'm working with Hyperlynx DRC Free Edition 6.5.1 and obviously I'm running into an issue when working with an imported layer stackup. The import command loads successfully my PCB stackup:

      But when I save the project file and reopen it, the stackup seems to be scrambled:

      Any ideas? Do I have a buggy stackup or is it a HLDRC bug?

      Even more interesting, the simulation works only with the "scrambled" stackup. With the original stackup the program crashes immediately.

      Regards

      Andreas

        • 1. Re: Hyperlynx DRC Stackup Issue? Or a bug?
          weston_beal

          Andreas,

           

          I've never seen anything like this, but I've heard that importing stackup files can be error-prone. Maybe we can help if we get more information about the path that lead to this situation. What program did you use to create the layout? Where did the stackup file come from?

           

          Because you mentioned that analysis with the original stackup caused the program to crash, and the "good" stackup looks so odd, I suspect that there is something wrong with the original layout data that came into DRC. Maybe there is some confusion in the layout data that caused some metal elements, such as traces or areafills, to be assigned to dielectric layers.

           

          With the imported stackup, it looks like some layers that are named DIELECTRIC are assigned as signal layers. In the Visibility and Colors tab, can you make all layers invisible, then make visible, individually each of the DIELECTRIC layers that are signal layers. See if it shows some structures on these layers. That will help find the problem.

           

          Regards,

          Weston

          • 2. Re: Hyperlynx DRC Stackup Issue? Or a bug?
            andreasdietz

            Hi Weston,

             

            thank you for your ideas. I'm working with PADS VX.2.2, Update 7 and Hyperlynx VX2.2 (this is where the stackup file came from). DRC version is 6.5.1.

            When I try to localize your mentioned artifacts, I'm running into a problem with the visibility switch for dielectric layers. I can change the colors and visibility for the metal layers only.

            Any ideas?

            Best regards, Andreas

            • 3. Re: Hyperlynx DRC Stackup Issue? Or a bug?
              weston_beal

              Andreas,

               

              Yes, you can only view metal layers. My thought was that since DRC shows some of the layers defined as signal layers, you should be able to view those layers. If that is not the case, then maybe the DRC design still has the dielectric layers defined correctly, but the GUI displays them incorrectly.

               

              I expect that this problem is data-dependent, so we might need to look into the design. I will contact you offline to talk about your specific data.

               

              Regards,

              Weston

              • 4. Re: Hyperlynx DRC Stackup Issue? Or a bug?
                weston_beal

                Andreas,

                 

                I was able to reproduce the error that described and a submitted a defect report for this issue. You can track the status of this DR through the link in the automated email message that the system should have sent to you.

                 

                In the meantime, it appears that you can safely edit the stackup information within DRC in the Layers spreadsheet view. Does that work for you? The better solution is to edit the layers in PADS before you export the design to DRC.

                 

                Send me a direct email message if you have any questions or concerns about this process.

                 

                Regards,

                Weston