I've been using uvm_hdl_force on other signals in my VHDL design no problem. However, my latest attempt doesn't work correctly. Here's the signal declaration in a VHDL module:
signal clk0_div1 : integer := 0;
and here's the force command:
The force works, it just sets it to 1, regardless of whether I use the above, 'hD, 13 or 'd13. The signal is inside a module that is instantiated using a GENERATE so I would understand if it just flat didn't work, but it's acting like the signal is a bit. Any ideas on why this isn't working?