8 Replies Latest reply on May 10, 2018 9:49 PM by qammarabbas313@gmail.com

    Hyperlynx DDR Wizard Pin Mapping

    qammarabbas313@gmail.com

      Hi,

      I am trying to run DDR3 batch simulation on Hyperlynx. I have assigned the ibis models to the controller and the DRAM (please find attached image), however when i do automatic net mapping the pins/nets of the controller become invisible. How can i assign controller nets to corresponding DRAM nets? Any help regarding the issue will be

      appreciated. Thank you!

       

       

       

       

       

      ibis.png

       

      Untitled.png

        • 1. Re: Hyperlynx DDR Wizard Pin Mapping
          weston_beal

          The important point here is that it appears from the net names that you are working in LineSim. If you have a Touchstone or SPICE circuit anywhere in your net topology that links multiple signal paths, then the DDRx Wizard net assignment can't find which controller pin is connected logically to each DRAM pin. You can create the correct logical connections by adding resistors. Connect a resistor to the two pins of the signal path through the SPICE circuit. You don't want the additional resistor to affect the signal, so change its value to 1 MOhm. Here is an example of what I described.

          The dashed red line shows a couple of signal paths. The connecting resistors are highlighted in yellow.

           

          Let us know if this is not the situation in your analysis.

           

          Regards,

          Weston

          • 2. Re: Hyperlynx DDR Wizard Pin Mapping
            qammarabbas313@gmail.com

            Thank you!

            I have one SDRAM chip and one controller currently. I have made connections using transmission lines. I am still not clear where to place the resistor. Should i connect it in series with the transmission line? For example, if i want to connect an address pin of controller to the corresponding pin of SDRAM. Please let me know what is the right approach?

            • 3. Re: Hyperlynx DDR Wizard Pin Mapping
              weston_beal

              If your circuit is connected with only transmission lines then you don't need to add resistors. That procedure applies to SPICE interconnect models.

               

              Looking more closely at the images in your initial post, it looks like the net assignment is working as expected. There are 2 things to consider:

              • When nets are assigned as part of the analysis, they are removed from the Controller Nets list.
              • The Controller Nets list has a filter at the bottom.

              In your case, the automatic net assignment has assigned Net133/Net132 as the first strobe diff pair and Net144/Net143 as the second strobe diff pair. That seems to be correct.

              The filter is looking for nets named *DQS* as would be found in a layout. Since there are no nets that match this filter, the Controller Nets list is empty.

              Notice that these net assignment pagesare shown as sub-pages of the DRAM Signals page. If the automatic net mapping works correctly, then the sub-pages are just for confirmation of the mapping. Also, change the net name filter to * when working in LineSim since we rarely change the name names there.

               

              Here are some good articles on Support Center about working with the DDRx Wizard. The one article in the link references many others.

              https://support.mentor.com/knowledge-base/MG250320

               

              Regards,

              Weston

              • 4. Re: Hyperlynx DDR Wizard Pin Mapping
                qammarabbas313@gmail.com

                Changing the net name filter to * helped as the net names are now visible. However, 4 nets corresponding to controller strobes are missing when i try to map controller(strobe) nets to DRAM nets. Does that mean that assignment is already done? Moreover, i cannot access the link given above. Kindly provide necessary guidance. Thank you!

                • 5. Re: Hyperlynx DDR Wizard Pin Mapping
                  weston_beal

                  when you assign nets to be part of the DDR analysis, they are removed from the Controller Nets list. This way, you don't assign a net to 2 different functions. It appears that your data strobe nets (differential) are already assigned as strobes as shown in your first image.

                   

                  In order to access the knowledge base article that I referenced, you need to log in to Support Center. If you don't already have an account on Support Center, I highly recommend that you start one. There is a treasure chest of useful information on that site.

                   

                  Regards,

                  Weston

                  • 6. Re: Hyperlynx DDR Wizard Pin Mapping
                    qammarabbas313@gmail.com

                    Hi,

                    If the nets have been assigned, why i cannot simulate them? Kindly find the attached image.

                     

                    x.png

                     

                    Could you please let me know why are these crosses appearing in the checkboxes? Thank you!

                    • 7. Re: Hyperlynx DDR Wizard Pin Mapping
                      weston_beal

                      The cross in the checkbox on that page indicates that the associated net is selected for analysis. You can unselect some of the nets and they won't be simulated. I use this for initial checks of the configuration. I run just a few nets of the bus to see if there are setup errors. When I have corrected the setup errors then I simulate all the nets of the bus.

                       

                      If a net cannot be simulated then there will be useful information in the log file about the cause.