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DDR Wizard's TM clock!

Question asked by on May 10, 2018
Latest reply on May 23, 2018 by weston_beal


I am trying to run DDR3 batch simulation on Hyperlynx. While making my timing model in the timing wizard, i see in the timing diagrams that the clock is single ended. Why is that so? Shouldn't the clock in DDR3 batch simulation be differential? Since the timing parameters in the datasheet are with reference to differential clock. Any help regarding the issue will be appreciated. Thank you!