3 Replies Latest reply on May 23, 2018 7:37 AM by weston_beal

    DDR Wizard's TM clock!



      I am trying to run DDR3 batch simulation on Hyperlynx. While making my timing model in the timing wizard, i see in the timing diagrams that the clock is single ended. Why is that so? Shouldn't the clock in DDR3 batch simulation be differential? Since the timing parameters in the datasheet are with reference to differential clock. Any help regarding the issue will be appreciated. Thank you!