I have a question to your Serdes expert and need an answer ASAP. see below:
I am currently simulating the attached simple channel in hyperlynx with Xilinx GTY transiever RX and TX IBIS-AMI files @ 6.144Gbps (Xilinx_UltraScalePlus_GTY_AMI_Kit_R1p0.zip)
I built the setup according to xilinx example (shown in their instructions document) . they use ADS.
when using the RX model in Hyperlynx, I cannot find ibis AMI RX equalizer (DFE) output port so I cannot capture the real behivour of the entire link at the receiver output. only receiver input pins (same as die) probes are available.
with other SWs it is possible to capture the eye diagrams at the receiver output as well as at the receiver input.
same problem occurs with the attached Ibis AMI file (FNSR_FTLF8529P3xxx_IBIS-AMI.zip). i uploaded it to this quary because its size is smaller than Xilinx_UltraScalePlus_GTY_AMI_Kit_R1p0.zip.
Do you know what is the problem here?
do you know how can I fix it?
does it happen with other Ibis AMI files as well?