1 Reply Latest reply on Jul 30, 2018 12:29 PM by dan_liddell

    ERC violations

    janardhan

      Hi,

       

      We are using a 16 nm design and are seeing ERC violations for filler cells in the switched (gated) domains.

       

      These filler cells are connected to the switched VDD and VSS.

       

      The ERC error is due to the floating gates of these filler cells. These filler cells actually form a device and require the gates to be connected to the rails.

       

      As the rails are connected to the always on VDD through the header switches, Calibre is not able to understand that these devices are connected.

       

      These filler cells are excluded from the source netlist.

       

      This ERC violation disappears when we use the following two statements in the SPICE (source) netlist.

       

      .GLOBAL VDD

      .GLOBAL VSS

       

      Are we allowed to use the two statements above in the source netlist? Does this mask the failure?

       

      Is there any way to fix these errors without using the two GLOBAL statements above?

       

      LVS is clean, only ERC is failing.

       

      Thanks.

        • 1. Re: ERC violations
          dan_liddell

          Hi,

           

          What kind of ERC violations are you seeing specifically? What is the rule?

           

          For this:

               "This ERC violation disappears when we use the following two statements in the SPICE (source) netlist.

           

              " .GLOBAL VDD

              " .GLOBAL VSS"

           

          ERC in Calibre only applies to layout circuit extraction, which doesn't consider the source netlist. So .GLOBAL in the source netlist has no effect on ERC.

           

          For this:

               "These filler cells are excluded from the source netlist."

           

          If these filler cells have devices in them, shouldn't the devices be represented in the source?

           

          dan