What kind of ERC violations are you seeing specifically? What is the rule?
"This ERC violation disappears when we use the following two statements in the SPICE (source) netlist.
" .GLOBAL VDD
" .GLOBAL VSS"
ERC in Calibre only applies to layout circuit extraction, which doesn't consider the source netlist. So .GLOBAL in the source netlist has no effect on ERC.
"These filler cells are excluded from the source netlist."
If these filler cells have devices in them, shouldn't the devices be represented in the source?