We are using a 16 nm design and are seeing ERC violations for filler cells in the switched (gated) domains.
These filler cells are connected to the switched VDD and VSS.
The ERC error is due to the floating gates of these filler cells. These filler cells actually form a device and require the gates to be connected to the rails.
As the rails are connected to the always on VDD through the header switches, Calibre is not able to understand that these devices are connected.
These filler cells are excluded from the source netlist.
This ERC violation disappears when we use the following two statements in the SPICE (source) netlist.
Are we allowed to use the two statements above in the source netlist? Does this mask the failure?
Is there any way to fix these errors without using the two GLOBAL statements above?
LVS is clean, only ERC is failing.