When I do the layout for the design, I have added the ports as well as port texts and they are visible in the layout. The layout is auto routed with no DRC errors too.
But while doing the LVS check the number of ports in the layout comes as zeros where as schematic indicates all the ports in the design (including VDD and GND).
I am new to using the mentor graphics tools and would appreciate any help in resolving the issue.
Following tools were used for layout and schematic
1. ADK_DAIC - Schematic
2. ADK_IC - Layout
3. Calibre - For LVS check.