4 Replies Latest reply on Aug 17, 2018 11:56 AM by chris_balcom

    LVS check fails saying number of ports are not matching in layout and schematic

    anakha

      When I do the layout for the design, I have added the ports as well as port texts and they are visible in the layout. The layout is auto routed with no DRC errors too.

      But while doing the LVS check the number of ports in the layout comes as zeros where as schematic indicates all the ports in the design (including VDD and GND).

       

      I am new to using the mentor graphics tools and would appreciate any help in resolving the issue.

       

      Following tools were used for layout and schematic

       

      1. ADK_DAIC - Schematic

      2. ADK_IC - Layout

      3. Calibre - For LVS check.

        • 1. Re: LVS check fails saying number of ports are not matching in layout and schematic
          chris_balcom

          Hi Anakha,

           

          Do you have sections in your log file/transcript that look like this example below, where label names and layers and cell names are listed? Are the port names you expected showing in either section? Are there any names at all showing in those sections for you?:

           

          --------------------------------------------------------------------------------

          -----              TEXT OBJECTS FOR CONNECTIVITY EXTRACTION              -----

          --------------------------------------------------------------------------------

           

          out (15.045,342.22) 11 top              vref (22.59,357.265) 11 top

          in (58.4225,357.265) 11 top            clka (94.2525,357.265) 11 top

          gnd! (132.375,353.27) 11 top            vdd! (134.0575,350.73) 11 top

           

           

          --------------------------------------------------------------------------------

          -----                                PORTS                                -----

          --------------------------------------------------------------------------------

           

          out (15.045,342.22) 11 top              vref (22.59,357.265) 11 top

          in (58.4225,357.265) 11 top            clka (94.2525,357.265) 11 top

          gnd! (132.375,353.27) 11 top            vdd! (134.0575,350.73) 11 top

          • 2. Re: LVS check fails saying number of ports are not matching in layout and schematic
            Community_Admin

            anakha - thanks for your post. I am going to move this over to the IC Design community. The Member Resources community is for general community questions and suggestions.

            • 3. Re: LVS check fails saying number of ports are not matching in layout and schematic
              anakha

              Hi,

              I could find only the following message from the transcript area.

              transcript_area.PNG

               

              I couldn't find any other log files. Please let me know your suggestions.

              • 4. Re: LVS check fails saying number of ports are not matching in layout and schematic
                chris_balcom

                Do you run Calibre from the command line or from the Calibre Interactive GUI ?

                 

                If from the command line, it could be in a file called "mylog" if used like this:

                 

                % calibre -lvs myrules | tee mylog

                 

                If you used Calibre Interactive GUI (maybe from your layout editor "calibre" menu button) then inside that GUI you should have a menu pulldown for:

                Transcript >> Echo Transcript to File >> "mylog"

                 

                "mylog" is just an example name I chose, your filename is likely different