Hi, I'm exporting the design from Altium to Hyperlynx to doing Vdrop simulation.
I'm not sure of results when I see the vias current density distribution.
I don't find the thickness of vias wall settings (hole copper plating). I need of this parameter
to check how much current goes into the via from current density.
Where I can set this parameter on Hyperlynx?
I'm using 9.4.1 version.
Thanks.
Ettore,
You can view and edit the plating thickness of via with the Options and the Padstack editor. See this Support Center article.
https://support.mentor.com/knowledge-base/MG591904
Notice the option for "vias are conductively filled" and Resistivity on the Default Padstack tab of the Preferences dialog. Those options affect the total resistance of vias, so are important for DC drop calculations.
Weston