Iam running DDRx Batch Simulation for DDR3-1866 with HyperLynxVX.2.3 and asking how to account the internal signal length of the controller.
The length matching within the layout is done with length information of the controller from vendor. So external signal length are different, depending on die-length.
1. Is it possible to add this length-information in Ibis or the Controller Model File?
2. Is it nescessary to add this information at all? Or is this handled by the automatic Write-levelling values?
Found no information in the SI / PI user Guide.
The internal signal length of the controller is represented in the IBIS file by the package definition. The Support Center article has some information about the package. https://support.mentor.com/knowledge-base/MG76593
The highest precedent package definition is always included in the circuit simulation, so the internal delays are included.