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Hyperlynx DDRx batch simulation and internal package length

Question asked by maddin on Sep 13, 2018
Latest reply on Sep 26, 2018 by weston_beal

Iam running DDRx Batch Simulation for DDR3-1866 with HyperLynxVX.2.3 and asking how to account the internal signal length of the controller.

 

The length matching within the layout is done with length information of the controller from vendor. So external signal length are different, depending on die-length.

 

1. Is it possible to add this length-information in Ibis or the Controller Model File?

 

2. Is it nescessary to add this information at all? Or is this handled by the automatic Write-levelling values?

 

Found no information in the SI / PI user Guide.

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