Hi community, I have a question regarding the packager behavior. First off, forgive me that I do not know the terminology very well. The issue that I am having is that when I place, say, an IC that has 2 AND gates contained inside and the symbol is a hetero or fractured type. In this instance I have two AND gates shown on my schematic, they both have been assigned to their own slots, and they both show a ref. des. of "U?". From what I understand, when I push this to the layout the Packager will run and assign reference designators to all the components of the design. Well, when I push the design to the layout, these 2 AND gates will not be assigned the same reference designator, they will be given separate ones meaning that 2 ICs have been put into the layout instead of a single IC which I wanted. Is there an option that I do not have checked? Is there a special way to place these components so that they will be inserted as a single device and not multiples? Below is a picture of before the packager. Since I am still in the middle of this design I will not be posting a picture of after running the packager, but the above description should be enough. In essence, you can imagine that when I run the packager, the AND gate on the left in slot 1 will be given the designator U1 and the other AND gate, which is in slot 2, will be given the designator of U2. What I want is for them to both be in the same package as U1.