7 Replies Latest reply on Oct 12, 2018 6:08 AM by robert_davies

    How to package a multi-gate IC into a single component. (VX2.x)


      Hi community, I have a question regarding the packager behavior. First off, forgive me that I do not know the terminology very well. The issue that I am having is that when I place, say, an IC that has 2 AND gates contained inside and the symbol is a hetero or fractured type. In this instance I have two AND gates shown on my schematic, they both have been assigned to their own slots, and they both show a ref. des. of "U?". From what I understand, when I push this to the layout the Packager will run and assign reference designators to all the components of the design. Well, when I push the design to the layout, these 2 AND gates will not be assigned the same reference designator, they will be given separate ones meaning that 2 ICs have been put into the layout instead of a single IC which I wanted. Is there an option that I do not have checked? Is there a special way to place these components so that they will be inserted as a single device and not multiples? Below is a picture of before the packager. Since I am still in the middle of this design I will not be posting a picture of after running the packager, but the above description should be enough. In essence, you can imagine that when I run the packager, the AND gate on the left in slot 1 will be given the designator U1 and the other AND gate, which is in slot 2, will be given the designator of U2. What I want is for them to both be in the same package as U1.







        • 1. Re: How to package a multi-gate IC into a single component. (VX2.x)

          You can always manually change the refdes and select the right slot


          OR do as explained below (from Dx user reference/manual)


          The Pkg Group= <groupname> property groups them into the same physical package without you having to manually assign a common reference designator. The Packager assigns the same Ref Designator to all symbols with the same Pkg Group property value. The Packager also preserves schematic-based slot assignments.


          The following list provides rules and considerations for grouping symbols into a common package:


               You can group symbols into one or more packages by assigning different Pkg Group attribute values, but all packages must be completely filled. If you try to assign more symbols to a group than will fit in one or more complete packages, the packager fails and reports that the device is not completely filled.


               Remove the Ref Designator from any already-packaged symbols you add to a package group.


               The PADS DX Designer tool performs the same DRCs on grouped symbols as on manually packaged or pre-packaged symbols.



          For each package you want to create:

               Double-click the first component you want to assign to the common package.

               In the Properties window, click the empty row at the bottom of the Property column, and select Pkg Group from the list.

               In the Value column, enter the string value you want to use to designate the package.

               Repeat until you fill the package.

          2 of 2 people found this helpful
          • 2. Re: How to package a multi-gate IC into a single component. (VX2.x)

            As phiet says you can assign a Pkg Group to each symbol to ensure they get assigned to the same package, this doesn't need the slots assigned to achieve this. But I am curious as to why you say you get them assigned to two different packages in the first case as the packager generally optimizes parts across the design, the only reason these two would be split is if there are three other slots in your design and probably on that page because packager usually optimizes across sheets well. The other reason it might not work is that your part definition in the library is incorrect. Are you using the integrated flow with Central Library or the Net List flow? If using the Net List flow then all of the packaging information is stored with the symbol and to ensure parts get packaged together the net list packager needs to be told how many symbols are in the package using the 'PARTS' property - so for a quad pack the property would be PARTS=4. This is not necessary in the integrated flow.

            BTW this is not a 'hetero' device in the PADS/PADS Pro meaning of such devices, this is just a multi-slot part (all slots are identical), hetero devices tend to be mixed gates or mixed representations of some sort (look them up in the documentation) or if you have access to SupportCenter look up https://support.mentor.com/en/knowledge-base/MG583318

            2 of 2 people found this helpful
            • 3. Re: How to package a multi-gate IC into a single component. (VX2.x)

              I am using the integrated flow. I noticed that while the packager may not need PARTS to have a value to package things together, the schematic tool needs it to assign pins correctly to parts. I made a dual buffer part symbol and didn't fill in the PARTS property and it paired the pins incorrectly when placed into the design. Like in slot 1 used pins 1 & 6 for input and output, respectively, and slot 2 used 3 & 4; it would place pins 1 & 3 for input and output for slot 1 and pins 4 & 6 for slot 2 until I said PARTS = 2 in the library symbol. I am only putting this here because it might be helpful for someone else to know. Thank you!

              • 4. Re: How to package a multi-gate IC into a single component. (VX2.x)

                The schematic editor does not need Parts either, there is something not correct in your symbol or part definition if it is mixing slots in this way, how do you place the parts into the scehmatic?

                • 5. Re: How to package a multi-gate IC into a single component. (VX2.x)

                  When I use multi-part devices I expand the part in the Databook and then select the slot I am wanting to use and then place them, that way they are already assigned a slot when I make the connections.

                  • 6. Re: How to package a multi-gate IC into a single component. (VX2.x)

                    I tend to agree with Robert that looks like something wrong with your pin mapping.

                    This is an example of our mutilple gate/slot part


                    • 7. Re: How to package a multi-gate IC into a single component. (VX2.x)

                      Then the slots should not be incorrect when you package them i.e. the pins should not be different from the pin mapping.