AnsweredAssumed Answered

DDR3 simulation with i.MX6 and Micrn DRAMs

Question asked by bgreenwald on Oct 22, 2018
Latest reply on Nov 6, 2018 by weston_beal

I am new to Hyperlynx,, and have only a smattering of simulation experience.  With persistence I was able to combine the right setups of IBIS models for the iMX6 processor and a pair of Micron 256 DDR3 DRAMS.  I have run the simulation for DDRx a few times, and each time all of the Addresses Failed.  Looking at the wave form of clock vs data, attached, it will be seen why.  The text at the bottom of the image, I added, and is what is shown when the cursor hovers over the triangle exclamation point icon on the report "Address" page tells what the simulation created as "virtual" wave forms ( see attachment).  Clearly the Data (yellow) transitions from 0 to 1 from 0.0M to 225.0M, while the clock (green) covers the span from -225.0M  to +225.0M,  It's biploar!  This, of course, is not right, but it is why the text says what it does.


What I want to know is why the data and the clock were created this way, within the simulation? Is it part of the IBIS model?

How can this be changed to both be single polar, so the simulation will be completely correct?  Change to IBIS or Hyperlynx settings?


Thank you