8 Replies Latest reply on Nov 6, 2018 7:26 AM by weston_beal

    DDR3 simulation with i.MX6 and Micrn DRAMs

    bgreenwald

      I am new to Hyperlynx,, and have only a smattering of simulation experience.  With persistence I was able to combine the right setups of IBIS models for the iMX6 processor and a pair of Micron 256 DDR3 DRAMS.  I have run the simulation for DDRx a few times, and each time all of the Addresses Failed.  Looking at the wave form of clock vs data, attached, it will be seen why.  The text at the bottom of the image, I added, and is what is shown when the cursor hovers over the triangle exclamation point icon on the report "Address" page tells what the simulation created as "virtual" wave forms ( see attachment).  Clearly the Data (yellow) transitions from 0 to 1 from 0.0M to 225.0M, while the clock (green) covers the span from -225.0M  to +225.0M,  It's biploar!  This, of course, is not right, but it is why the text says what it does.

       

      What I want to know is why the data and the clock were created this way, within the simulation? Is it part of the IBIS model?

      How can this be changed to both be single polar, so the simulation will be completely correct?  Change to IBIS or Hyperlynx settings?

       

      Thank you

      Bill

        • 1. Re: DDR3 simulation with i.MX6 and Micrn DRAMs
          Community_Admin

          bgreenwald - thanks for your post. All Mentor Ideas spaces are for enhancement requests for other customers to vote on and that the product teams can consider for future releases. And where you posted your question is for customers to suggest new ideas spaces for other Mentor products. So I am going to move your post to the HyperLynx community where it will receive greater visibility by other customers.

          • 2. Re: DDR3 simulation with i.MX6 and Micrn DRAMs
            weston_beal

            bgreenwald,

             

            The M multiplier should be m. All the voltages are in mV. The clock is differential, so that looks correct. It would be good if the peaks extended to +/- 400mV, but that's another issue.

             

            The problem is that the address signal doesn't go above the Vinh_ac threshold, which should be around 825mV. The signal is pulled down to 0V. Most likely, you need to go to menu Setup > Power Supplies ... and define the voltage of the termination net (0.75V?). HyperLynx attempts to assign voltages from net name like 5V0, but VTT doesn't tell anything about the number.

             

            Regards,

            Weston

            • 3. Re: DDR3 simulation with i.MX6 and Micrn DRAMs
              bgreenwald

              Weston;

               

              I looked into what you specified and corrected to power signals that were only alpha characters, from “0” to their correct value.  I was surprised that I could not make the changes in the pull down Setup window “Power Supplies”, and that only integers were allowed.  What I did was find the entries for Net Name vs. Voltage list in the .bbd and .bud files, and changed them there.  After the .bud file was done, the new values showed up in the window, and the address sim results Passed.  I know now that these alpha only voltage signals need to be corrected as part of the setup for simulation.

               

              Please explain why the simulator does not use the actual voltage on these signals.  For instance, the DDR_REF signal is the reference voltage for the RAMs. It’s normal value is 0.675V, yet it is represented in the simulator as a 1V.

               

              Bill Greenwald

              • 4. Re: DDR3 simulation with i.MX6 and Micrn DRAMs
                weston_beal

                Bill,

                 

                Your experience does not correlate with mine. You should be able to edit the power supply net voltages in the dialog box. Specify in the top area which nets are power supply nets. Specify in the bottom area the correct DC voltages for the previously designated power supply nets. There is no need to edit the BUD file. In fact, editing the BUD file is strongly discouraged.

                 

                Open the tool help documents, BoardSim User Guide and look for the section titled, Verifying That Power Supply and Signal Nets are Recognized Correctly. That should help explain the power supply net setup.

                 

                Regards,

                Weston

                • 5. Re: DDR3 simulation with i.MX6 and Micrn DRAMs
                  bgreenwald

                  Well, I had no other choice.  I could type the number in, but it would not take and I always got the message about only numbers in the range -999 to 999 would work.    Is the ability to edit only usable if you have a full license?  We are working on a 30 day demo until our purchase goes through.

                   

                  I did make sure the proper net name were included.

                   

                  Can you tell me when the .bbd and .bud files are created?  Is there another file that contains the list of net names and their associated supply voltages?

                   

                  Bill

                  • 6. Re: DDR3 simulation with i.MX6 and Micrn DRAMs
                    bgreenwald

                    Weston;

                    I just saw the “do not edit” warning in the files because they are re-written by boardsim.  I did keep the original, though.

                    I did edit them before opening the board project file and the changed numbers were fine, and remained intact with each re-write.

                     

                    Bill

                    • 7. Re: DDR3 simulation with i.MX6 and Micrn DRAMs
                      bgreenwald

                      Weston;

                      Hello, again.  Thank you for solving my previous failure issue.  I have another issue that needs to be explained.  I hope you can help.

                       

                      I am doing more simulations on the same processor and micron ram setup, and a different (Nanya) RAM, and have had failures in the READ simulation of fast corner, on specific byte lanes;

                      Nanya: D0:D15 and D48:D55

                      Micron: D0:D7 and D48:D55

                       

                      The triangle “!” note, in the report, reads; “Multi-threshold for strobe net is found!!! Calculation of setup/hold time is cancelled for this net!”  Looking at the waveform there are 2 threshold sets for the setup and hold margins.

                      Nanya RAM:

                      Setup: .835000m, .515000m

                      Hold: .765000m, .585000m

                      Checking the waveforms of the “good” data bits the lower of the 2 is the only threshold.

                       

                      Micron RAM:

                      Setup: .835000m, .515000m

                      Hold: .765000m, .585000m

                      These are the same as the Nanya RAM, which would indicated that the numbers come from the “common” element, the processor.

                       

                       

                      I looked in the IBIS files for the processor and the rams and did not find those numbers in the models I have chosen for the simulation.

                       

                      I did find the following note in the Nanya IBIS file and wonder if it is related.

                       

                      |NOTE: If using the IBISCHK 4.2.1 or older parser, Differential receiver

                      |threshold parameters must be commented out because the parser generates

                      |errors for multiple differential models.

                       

                      Likewise I found this note in the Micron IBIS file.

                       

                                    - When running through ibischk4.2.1 or older parsers, this

                                       file will contain errors related to the Differential

                                       Receiver Thresholds. These errors can be fixed by

                                       removing comment characters '|' in DQS_* and CLKIN_* models

                                       in front of Single-ended Receiver Thresholds parameters and

                                       removing the Differential Receiver Thresholds parameters.

                       

                      Do you understand what is happening?  Why is the failure on specific byte lanes, where do the multiple thresholds come from.  I am hesitant in editing the IBIS files as the 2nd note suggests.

                       

                      Thank you for your time.

                       

                      Bill Greenwald

                       

                       

                       

                       

                       

                       

                       

                       

                       

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                      • 8. Re: DDR3 simulation with i.MX6 and Micrn DRAMs
                        weston_beal

                        Bill,

                         

                        Most likely, you just need to change the measurement point. The processor package is fairly big so the signal at the pin includes reflections from the die. Therefore, the strobe signal crosses the threshold voltages more than once per transition. The waveform at the die should be smooth through the transition and will result in good measurements. See this article for details on how to make this change depending on which version of HyperLynx you are using.

                        https://support.mentor.com/en/product/861057060/knowledge-base/MG603827?pid=sc%3Asearch&pid_context=timing_location/know…

                         

                        Weston