I've been pushing my group to remove unused pads on internal layers to try and remove some of the voids created by vias + clearance values.
Until today.. One of my group tried removing unused pads on internals under his BGA which had a rule area defined.
Much to our surprise many of the signals inside the rule area dropped the vias completely on the internals when they were needed so we had dead end traces.
Trying to DRC against the board revealed multiple hangers and partial nets, funny thing is it did not report missing pads.'
Lucky thing is the DRC picks it up..
Any Ideas? this one seems a bit scary to me..